Abstract: According to one embodiment, a method for storing content addressable memory (CAM) mask values may include storing mask values according to mask size in a mask register set (200). A mask register set (200) may include a number of locations arranged into regions (202, 204, 206 and 208). Each region (202, 204, 206 and 208) can store mask values of a different predetermined size.

Abstract: A system is provided for testing a physical layer device, or various network portions connected to that physical layer device. The test system includes a random bit generator that, during use, produces a random pattern of bits clocked in parallel onto the transmit portion of the physical device. The parallel-fed information can then be serialized and selectably fed back to the receive input of the same physical device. The receive portion of the physical device can then deserialize the random pattern of bits, and present those bits to logic within the test system. The test system can, therefore, compare each of the random pattern of bits presented to the physical device with corresponding bits derived from the deserializer. If each bit within the random pattern of m bits forwarded to the serializer does not compare with each corresponding m bits forwarded from the deserializer, then the physical device is known to be a failure.

Abstract: An electro-optical apparatus constructed according to various inventive principles disclosed herein provides flexibility in the type and arrangement of components. The electro-optical apparatus preferably includes a Printed Circuit Board (PCB). An interface device can be electrically connected to the PCB, and an electro-optical device can be electrically connected to the interface device. A lens is preferably arranged in optical communication with the electro-optical device. Numerous variations in component selection and arrangement are contemplated within the scope of these inventive principles. Various methods for configuring an electro-optical apparatus are also provided.

Abstract: A method is described for forming a trench in a semiconductor substrate, which has a silicon layer, an oxide layer overlying the silicon layer, and a nitride layer overlying the oxide layer. The method includes etching the nitride layer to a nitride end point using a nitride etching chemistry, which includes a fluorinated hydrocarbon, oxygen, and an inert gas selected from the group consisting of neon, argon, krypton, xenon, and combinations thereof. Methods of making semiconductor devices, methods of reducing defects in semiconductor devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods for forming a trench are also described.

Abstract: A method of making a structure, includes filling a via hole with a conductive material, to form a via. The via hole passes through an etch-stop opening. In both directions along a first axis dielectric material is present between the via hole and edges of the etch-stop layer, and in both directions along a second axis, perpendicular to said first axis, dielectric material is not present between the via hole and edges of the etch-stop layer.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a plurality of control signals and a select signal, in response to (i) a receive clock signal, (ii) a reference clock signal and (iii) a master clock signal. The second circuit may be configured to generate a read signal and a window signal in response to the plurality of control signals. The third circuit may be configured to generate a lock signal in response to (i) the reference clock signal, (ii) the select signal, (iii) the read signal and (iv) the window signal. The receive clock signal and the reference clock signal may be independent clocks configured to provide range control over one or more channels.

Abstract: Semiconductor process yield analysis in which the relationship between a wafer-level parameter and a die-level parameter is evaluated can be performed more quickly and with greater accuracy than has been the case with previous such yield analysis. The yield analysis can be performed by selecting regions of a semiconductor wafer or wafers from which parametric data is to be obtained for use in the analysis, based on one or more characteristics of the wafer(s). The yield analysis can be performed by grouping the parametric data based on both a grouping of the wafer-level parametric data and a grouping of the die-level parametric data. The yield analysis can be performed by grouping the parametric data in greater than 3 groups.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first select signal, a second select signal and a first data stream in response to an input data stream and a redundancy signal. The second circuit may be configured to generate an output data stream in response to the first data stream, the first select signal and the second select signal. The second circuit may be configured to replace one or more characters of the first data stream.

Abstract: In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to adjust a threshold voltage of the transistor. By masking a portion of the active region, the dopant is substantially prevented from getting in a region near an edge of the trench. Among other advantages, this results in reduced leakage current.

Abstract: A pulse width position modulator (PWPM) includes a digital delay circuit that outputs multiple subclocks according to a native pixel clock. The multiple subclocks are each skewed within different time periods of the native pixel clock period. A skew pulse generator receives the multiple subclocks from the digital delay circuit and outputs multiple subpixels according to different logical combinations of the multiple subclocks thereby providing increased subpixel output resolution using the native pixel clock. A clock skew synchronizer aligns the subpixels with a line synchronization signal. The clock skew synchronizer allows lines in a printed image to be aligned with the line synchronization signal within subpixel resolution without using high frequency sampling circuity.

Abstract: A method for interconnecting a plurality of dies. The method generally includes receiving a plurality of interconnect requirements for the dies. The interconnect requirements may include a priority for each of a plurality of nets. A position and an angle for one of the dies relative to a substrate may be calculated in response to the interconnect requirements. A plurality of nets may then be routed among the dies and a plurality of substrate pads defining external connections for the substrate. The dies may be mounted to the substrate after routing has been finalized.

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: Embodiments of the present invention relate to an electronic device having programmable chip enable inputs in that each chip enable has a programmable assertion level, e.g., high or low. The device may be an integrated memory chip, e.g., SRAM device. On power up, a JTAG input port of the electronic device can be used to program a configuration register which contains bits for setting the assertion level of each chip enable input. The bits may be used to control respective multiplexers which select between a chip enable signal and its inverse. The chip enable signals may originate from a controller device. Regarding a memory device, the outputs of the multiplexers are coupled to chip enable signals of an integrated memory core.

Abstract: A system (100) may include a content addressable memory (CAM) device (102) and at least two requesting devices (104-0 and 104-n). Requesting devices (104-0 and 104-n) and a CAM device (102) may be connected by at least two communication links (106-0 and 106-n). A CAM device (102) may generate responses to requests, and assign a flow identification value for responses based on a communication link (106-0 and 106-n) on which a corresponding request was received.

Abstract: In one embodiment, a transistor comprises raised structures over a source region and a drain region. The raised source structures may comprise selectively deposited metal, such as selective tungsten. A self-aligned contact structure formed through a dielectric layer may provide an electrical connection between an overlying structure (e.g., an interconnect line) and the source or drain region. The transistor may further comprise a gate stack having a capping layer over a metal.

Abstract: The present invention cascaded optical switching system includes architectures that provide three dimensional optical signal beam steering utilizing two dimension optical signal beam steering devices. A plurality of cascaded optical switches form a cascaded multi-dimensional optical switch fabric and direct an optical signal beam from one of the plurality of optical switches to another of the plurality of optical switches in a different dimension. In one embodiment, an incidence corrective device is included in a cascaded optical switch fabric and directs an optical signal beam in a shallow angle so that it strikes the next optical switch at a corrected incidence angle. A corrected incidence angle permits an optical signal beam to be forwarded at a relatively shallow angle to an optical switch located in a relatively close proximity on the optical switch fabric. The present invention also provides for refocusing of spreading optical signal beams and mitigation of signal loss.

Abstract: In one embodiment, a transistor is fabricated by forming a sacrificial emitter over a base, forming an oxide layer over the sacrificial emitter, removing a portion of the oxide layer, and then removing the sacrificial emitter. An emitter is later formed in the space formerly occupied by the sacrificial emitter. The sacrificial emitter allows a base implant step to be performed early in the process using a single masking step. The base may comprise epitaxial silicon-germanium or silicon.

Abstract: In accordance with one embodiment of the present invention, a circuit provides power stability functions for a microcontroller, during startup and normal operations performing power on reset functions and an array of power stability functions. The power on reset functions hold the microcontroller in a safe reset condition, reinforce the POR hold, and force its switch mode pump to drive up voltage provided to its common supply source. The power stability functions constitute a power on reset function, a power supply health, e.g., power state condition monitoring function, a control function for dynamically controlling the common supply source, and auxiliary functions, which may be protective of a flash memory. The power on reset function operates at a fixed and/or programmably changeable voltage levels. In one embodiment, the POR circuit is interconnected with a processor through a bus, enabling programmatic processor control of microcontroller power through interaction with the POR circuitry.

Abstract: A polishing system is provided which includes an o-ring adapted to couple a carrier ring to a carrier plate. In some embodiments, one component may include a groove with which to receive the o-ring and the other component may be substantially absent of a groove adapted to receive an o-ring. Alternatively, both components may include a groove with which to receive the o-ring. Consequently, a semiconductor polishing system component comprising a notch adapted to receive an o-ring is also provided herein. In particular, the semiconductor polishing system component may be adapted to couple to another semiconductor polishing system component by use of the o-ring. In addition, a method for assembling a semiconductor polishing system is contemplated herein, which includes positioning a first component of the semiconductor polishing system against a portion of an o-ring protruding from a groove arranged within a second component of the semiconductor polishing system.

Abstract: A method of forming a photoresist includes forming a photoresist and patterning/developing it according to conventional methods. The photoresist is then subjected to ion implantation. The ions may be selected from the group consisting of argon, boron, boron fluoride, arsenic, phosphorous and nitrogen. The ion implantation during processing of the photoresist provides a stabilized photoresist and helps reduce CD loss, loss of the photoresist and formation of pin holes and striations.