Abstract: A method is provided for processing a semiconductor topography. In an embodiment, the method includes polishing the topography on a primary polishing pad during a primary polishing step without depositing water on the primary polishing pad. The method may also include transferring the topography from the primary polishing pad to a final polishing pad. A substantial amount of residual slurry particles may be present on the topography while the topography is being transferred. In an embodiment, the method may also include polishing the topography on a final polishing pad during a final polishing step. The final polishing step may include depositing water on the final polishing pad in a plurality of dispense intervals to reduce a rate of change of a pH of a polishing solution on the topography.

Abstract: A programmable logic device comprising one or more horizontal routing channels, one or more vertical routing channels, and a logic element. Each logic element may be configured to connect between one of the horizontal routing channels and one of the vertical routing channels. The logic element may comprise a logic block cluster and a memory block.

Abstract: One embodiment disclosed relates to a chemical-mechanical polishing process. The process includes performing chemical-mechanical polishing on an entire wafer lot without look ahead polishing of a first article wafer. A normalized polish rate is determined, and a process time for a next wafer lot is predicted using the normalized polish rate. Another embodiment of the invention relates to a polishing apparatus for chemical-mechanical planarization of semiconductor wafers.

Abstract: The invention enables construction of a microscope that has one or more advantageous characteristics as compared to previous microscopes. The microscope can be small and lightweight and, in particular, sufficiently small and light weight to be portable (e.g., smaller and far lighter than probe station microscopes used for microscopic liquid crystal analysis of a semiconductor device). The microscope can include a small and lightweight bellows that provides zoom capability. The microscope and/or a tripod that is used with the microscope can be implemented to provide objective lens position control capability (with any number of translational and/or rotational degrees of freedom). The microscope can include apparatus for ejecting a hot gas from the microscope to heat a specimen being observed with the microscope.

Abstract: A circuit that permits a processor in a microcontroller to adjust its clock speed on the fly. A processor receives a current clock signal and a phased current clock signal from a speed selection switch. A new speed selection switch provides a new clock signal and a phased new clock signal for comparison with the current clock signals. When the states of the current and new clocks appropriately align after issuance of a control from the processor, the new speed is switched into the current speed switch to permit the clock speed to change without producing spurious signals that cause unpredictable action in the processor. This advantageously allows the microcontroller to adjust its clock speed under program control.

Abstract: A non-integer order controller for providing stability in a circuit. The non-integer order controller may be in either a feed-forward path or a feedback path of the circuit. Thus, the non-integer order controller is operable to provide stability for the circuit. The closed loop system may be a phase lock loop.

Abstract: A method and system for testing the logic of a complex digital circuit containing embedded memory arrays. One embodiment provides for a process which first creates a model for the memory array in the circuit. Next, the memory array is loaded with values representing the model. For example, the memory array may be modeled as a wire by loading each memory location with its address. In this fashion, the data output of the memory array will be equal to the input address. Next a test pattern is generated, based upon the model of the memory array. The memory array is prevented from being written while the test pattern is scanned into the circuit. In this fashion, the output of the memory array is predictable and the output of the circuit may be monitored to determine if the combinational logic has any defects.

Abstract: The method of the present invention acquires delay, setup and hold values that appropriately reflect the timing characteristics of an integrated circuit represented by a cell file. A data and clock input slope pair is selected and the data setup time value is swept with respect to the clock. For each setup value a corresponding hold value is determined for functional failure. Then for each setup and hold value pair a delay value is ascertained. In one exemplary implementation optimal delay, setup and hold values are determined and utilized to facilitate higher frequency designs using the same physical cell layout library.

Abstract: Embodiments of the present invention relate to a method and mechanism for testing wire bonds in an integrated circuit package. The method comprises bonding an integrated circuit silicon die to a package substrate. Next, wire connections are formed between pads in the integrated circuit silicon die and contact leads in the package substrate and testing each of the wire connections in order to detect non-stick failures using electrical continuity provided by the integrated circuit silicon die substrate. Electrical continuity is provided through dedicated pads in the package substrate that contact the underside of the silicon die substrate. The dedicated contact pads in each package substrate of the molded laminate array are connected to each other and to the mold gate. The continuity thus provided allows a non-stick-on-pad test by ensuring continuity between the wire spool through the die to the mold gate.

Abstract: A method of forming an essentially uniform doped insulating layer is disclosed. Variations in a substrate temperature that may result in a dopant gradient within a doped insulating layer can be compensated for by varying a dopant supply rate in a deposition process. One particular embodiment discloses a method of forming a high density plasma phosphosilicate glass having a phosphorous concentration of 8% or greater by weight that varies by no more than about 1% by weight throughout.

Abstract: An apparatus comprising a first arbiter cell, a second arbiter cell and a selection device. The first arbiter cell may be configured to lock if one or more requests are not resolved within a first predetermined time period. The second arbiter cell may be configured to dominate if the first arbiter cell enters a metastable state. The selection device may be configured to provide arbitration between the first and second arbiter cells within a second predetermined time period.

Abstract: A method and system dynamically controlling microcontroller power. In one embodiment, the method and system configures a microcontroller power state, senses its condition, and determines its suitability status, communicates that status between a POR circuit and a processor, controls certain microcontroller functions accordingly, and dynamically programs power related functions. This is enabled, in one embodiment, by dynamic interaction between the POR circuit and the processor. Microcontroller power status is ascertained, and a corresponding optimal power state determined. Optimal values for programmable independent multiples of a supply voltage is programmatically calculated and set, dynamically adjusting microcontroller power states. In one embodiment, the optimal values are communicated to a scaler in the POR circuit by the processor, and registered within a multiplexer/register matrix within the scaler.

Abstract: The present invention is an efficient system and method for cascading optical switches. A plurality of cascaded optical switches form a cascaded optical switch fabric and direct an optical signal beam from one of the plurality of optical switches to another of the plurality of optical switches. In one embodiment of the present invention, a variable incidence corrective device is included in a cascaded optical switch fabric. The incidence corrective device directs an optical signal beam in a shallow angle so that it strikes the next optical switch at a corrected incidence angle. A corrected incidence angle permits an optical signal beam to be forwarded at a relatively shallow angle to an optical switch located in a relatively close proximity on the optical switch fabric. The present invention also provides for refocusing of spreading optical signal beams and mitigation of signal loss.

Abstract: The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform.

Abstract: An integrated circuit includes a test circuit that may be configured to generate a test signal having a predetermined pulse width in response to a control input. The test signal may track process corners of the integrated circuit and may be used to predict a failure of the integrated circuit.

Abstract: A low offset voltage buffer which comprises a first, second, third and fourth MOS device, each comprising a gate, a source and a drain; a current source coupled to the drains of the first and second MOS devices; a current sink coupled to the sources of the third and fourth MOS devices; an input coupled to the gate of the third MOS device and an output coupled to the source of the first MOS device. The source of the first MOS device is coupled to the drain of the third MOS device and the source of the second MOS device is coupled to the drain of the fourth MOS device. The voltage buffer can also be implemented in both NMOS and PMOS devices.

Abstract: A circuit and method for controlling a spread spectrum transition are presented comprising a first circuit and a second circuit. The first circuit may be configured to generate a clock signal in response to (i) a reference signal, (ii) a sequence of spread spectrum ROM codes, and (iii) a command signal. The second circuit may be configured to synchronize the command signal to a feedback signal. The sequence of spread spectrum ROM codes may be generated according to a predetermined mathematical formula and optimized in accordance with predetermined criteria.

Abstract: An apparatus having an interface connectable to a network. The interface may be configured to transmit information via a frame in the network. The frame may have a packet envelope carrying a plurality of packets. A first packet may have one or more labels configured to control routing of the first packet through the network and a payload to carry the information.

Abstract: An apparatus comprising a circuit having one or more inputs. The one or more inputs may be configured to provide a device identification (ID) of one or more different device IDs. The one or more inputs may allow implementation of the circuit with one of the one or more different device Ids.

Abstract: In one embodiment, an environment for testing integrated circuits includes a first die coupled to a tester. The first die includes a removable connection configured to couple a signal from the first die with an adapter layer to a second die being tested. The removable connection may be an elastomeric interposer or a probe, for example.