Abstract: A method of testing, in parallel, a memory device including a plurality of memory cells organized into memory blocks, the memory device having a plurality of wired-OR pre-charged differential data line pairs, includes the steps of enabling a predetermined number of memory blocks at a time; writing to and reading as many bits as the predetermined number of enabled memory blocks in parallel; and detecting when both data lines of each of the wired-OR differential pairs are active at a same time, indicating that at least one bad memory cell exists within at least one of the predetermined number of enabled memory blocks.

Abstract: A memory device includes a memory array having bit line pair interface connections being made alternatively at each side of the array. Column redundancy bit line pairs may be directed to either side of the array. In addition, bit line loads are placed at both ends of respective bit line pairs to improve speed. Stated differently, the memory device includes a bit line pair accessible from either of two sides of the memory array. The array may be one of a number of blocks within the memory device, while the bit line pair may comprise a redundant column bit line pair. The two sides of the memory array from which the bit line pair is accessible may be opposite sides of the array. In addition, the memory device may also include interdigitated bit line pairs within the memory array. One or more bit line pairs, including the above-mentioned redundant column bit line pair, may have bit line loads (e.g., transistors) at each end.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an output signal having a first frequency in response to (i) an input having a second frequency and (ii) a first control signal. The second circuit may be configured to generate the second frequency in response to (i) a plurality of third clock signals and (ii) a second control signal. The third circuit may be configured to present the first and second control signals in response to one of said plurality of third clock signals.

Abstract: A circuit for generating a pulse including a scan register having a first scan bit; first logic device receiving a first signal and generating a second signal; and a programmable delay circuit coupled to the scan register and the first logic device. The programmable delay circuit receives the second signal and generates a delayed second signal after a programmable period of time. The programmable period of time is determined by the first scan bit. The circuit also includes a logic circuit that recevies the second signal and the delayed second signal. The logic circuiit outputs the pulse having a pulse width proportional to the programmable period of time.

Abstract: An electrically erasable programmable read only memory (EEPROM) cell including a tunnel dielectric layer formed over a semiconductor substrate. The EEPROM cell may have a floating gate transistor and a select transistor. The floating gate transistor may have a floating gate formed over the tunnel dielectric and a control gate formed over the floating gate. The select transistor may have a first gate formed over the tunnel dielectric and a second gate formed over the first gate. The second gate may be electrically connected to the first gate.

Abstract: A circuit and method comprising a physical layer circuit, a select circuit and a repeater circuit. The physical layer circuit may be configured to present a number of shared signals and a number of individual signals. The select circuit may be configured to connect one or more said first number of shared signals to one of a second number of shared signals, where the second number of shared signals may be less than the first number of shared signals. The repeater circuit may be configured to receive the number of individual signals and the second number of shared signals.

Abstract: An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the fist output signals and to produce second output signals indicative of logic states of the first output signals therefor The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry.

Abstract: A test device for testing an integrated circuit fabricated according to a process is disclosed. The device includes a layout structure, and a excitation circuit. The layout structure includes a plurality of branch structures which are arranged in parallel. Each branch structure includes a feature having a predetermined dimension. The dimension of the feature between associated with adjacent branch structures increases/decreases so as to cover an entire, predetermined spectrum or range of predetermined minimum dimensions. The feature is present (i.e., formed) in a respective branch structure when the process bias/resolution supports fabrication of that dimension. Otherwise, that feature is absent. The excitation circuit is adapted to provide a current through each branch structure to the extent the feature in the branch structure is present. All the branch currents are collected at a common node. If the feature is absent, the current will not be carried, and will thus not contribute to the total current.

Abstract: A buffer circuit or output driver can produce a common-mode output and maintain fully differential input signals to the buffer. The common-mode output is derived by shifting the input voltages to the buffer by a threshold amount, averaging the shifted input voltages through a resistor divider, then again-shifting the resulting voltage to an output node of the buffer. The voltages at which the first and second shifts occur are equal but in opposite direction. Accordingly, the output voltage is at a midscale, average or common-mode voltage of the input voltages applied to the buffer. The output voltage has sufficient swing head room and is well suited for low power applications. The buffer circuit utilizes relatively few transistors and only two major current paths from the power supply to ground. Accordingly, the buffer consumes relatively low amounts of power.

Abstract: An improved door closure indicator is provided. The indicator operates on pressure levels read within a pressurized chamber rather than from proximity switches coupled between the chamber and the door. If the door seals to the chamber, pressure within the chamber will quickly change, and the change will be read on a pressure sensor indicative of the door closure. According to one example, the chamber can comprise a vacuum chamber and the pressure sensor can be a vacuum monitor. Once vacuum is detected, it is determined with more absolutism that the door is actually closed rather than having to rely upon switch operation and/or alignment of the door activation mechanism to proximity switches arranged on the chamber housing.

Abstract: A communication unit, coupled to a communication link, may be enabled if a signal is present on the communication link and the unit is active. However, if no signal is present on the communication link, the communication unit generates a token used to activate another communication unit coupled to another communication link. This token may be generated after a delay which allows the communication unit to wait some time for the signal to appear on the communication link before generating the token. Where a communication unit has been activated and enabled, that communication unit may receive signals from the communication link or transmit signals onto the communication link. Selecting a first communication unit from a number of communication units to be activated may be accomplished by coupling one of the communication units to a start-up circuit. The start-up circuit provides a start-up token to activate the first communication unit.

Abstract: A device and method for interconnecting two universal serial buses (USBs) is provided in which the device controls the current supplied to the device from the USBs via a power manager. In particular, when one or both of the buses connected to the device enter a suspended state, the power manager reduces the current consumed by the device so that the device does not exceed a maximum suspend current. The device may also have a power manager controller which permits one or both device drivers connected to the USBs to control the power manager.

Abstract: An apparatus comprising a storage circuit, a load circuit and an oscillator circuit. The storage circuit may be configured to store a number of configuration bits configured to provide one or more control signals. The load circuit may be configured to provide a variable magnitude load in response to the one or more control signals. The oscillator circuit may be configured to provide an output signal, where the output signal has (i) a frequency determined in response to the magnitude of the load circuit and (ii) a magnitude generated in response to a current generated in response to an output of a clamp circuit.

Abstract: A phase detector circuit comprising a control circuit, a pump-up circuit and a pump-down circuit. The control circuit may be configured to generate a control signal in response to (i) a data signal, (ii) a half-rate clock signal, and (iii) a quadrature of the half-rate clock signal. The pump-up circuit may be configured to generate a pump-up signal in response to (i) the data signal, and (ii) the control signal. The pump-down circuit may be configured to generate a pump-down signal in response to (i) the pump-up signal and (ii) the control signal.

Abstract: A nonvolatile cell comprising a first device comprising a first transistor type and a second device comprising a second transistor type. The first device may have a gate, a source, a drain and a gate oxide layer over the gate. The second device may have a gate, a source, a drain and a floating gate formed between the gate of said first device and the gate of the second device. The floating gate may be configured to store a charge in response to (i) a first voltage applied to the source and drain of said first device and (ii) a second voltage applied to the source and drain of the second device.

Abstract: A circuit and method comprising (a) a first circuit configured to generate an output signal having a variable pulse width in response to an (i) input signal and (ii) a control signal and (b) a second circuit configured to generate the control signal in response to (i) the input signal and (ii) a test input. In one example, the first circuit may comprise a register configured to present the output signal and an edge detection circuit configured to present a second control signal to said second circuit. In another example, the second circuit may comprise a plurality of first gates that may generate the output signal in further response to the second control signal.

Abstract: An apparatus comprising a first circuit, a reset circuit and an output circuit. The first circuit may be configured to generate one or more state signals in response to (i) a first and a second write control signals and (ii) one or more control signals. The reset circuit may be configured to generate the one or more control signals in response to (i) a global write signal and (ii) the first and second state signals. The output circuit may be configured to generate a third and fourth write control signal in response to (i) the global write signal (ii) a data input signal and (iii) the first and second state signals. In one example, the third and fourth write control signals may generate a pulse on either the third or the fourth write control signals in response to a transition of the data input signal.

Abstract: A NOR gate including a pull-down circuit coupled to a pull-up circuit. The NOR gate is configured to drive an output signal to a low logic state at a substantially uniform slew rate regardless of the number of input signals that are in high logic state. The pull-down circuit may include a first plurality of transistor circuits each coupled to a corresponding one of the plurality of input signals, and a second plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The first and second plurality of transistor circuits may each include an n-channel MOS (NMOS) transistor. The NOR gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the set-up and hold time window of the input path circuit.

Abstract: A circuit and method comprising a first logic circuit, a second logic circuit and a speed detect circuit. The first logic circuit may be configured to present a global signal in response to a plurality of first speed indication signals. The speed detect circuit may be configured to present a plurality of second speed indication signals in response to an input operating at one of a plurality of speeds. The second logic circuit may be configured to present a plurality of internal speed indication signals, each in response to (i) the global signal and (ii) one of the plurality of the speed indication signals.

Abstract: An architecture for data correction that may be used in non-volatile random access memories. In one embodiment, a circuit configured to be responsive to a control signal and to provide bitline outputs in response to bitline inputs is provided. The states of the bitline outputs depend upon the states of the bitline inputs and the control signal. The control signal may be provided by a non-volatile static random access memory (SRAM) cell. The circuit may include inverting and non-inverting paths or may include crossing and passing circuitry. The crossing and passing circuitry connects a first input of the circuit to a second output of the circuit in response to a first state of the control signal and further connects the first input to a first output of the circuit in response to a second state of the control signal. The control signal may be generated by a control device such as a non-volatile random access memory cell.