Abstract: A capacitive sensor array may comprise a plurality of column sensor electrodes and a plurality of row sensor electrodes. The column sensor electrodes may be capacitively coupled with the row sensor electrodes to form a plurality of unit cells each including an intensity center identifying a location of greatest capacitance sensitivity between a row electrode and a column electrode. An axis of a set of row sensor electrodes may cross at least a portion of each row electrode in the set, and the intensity centers associated with the row electrodes in the set may be staggered on alternating sides of the axis. For each of the plurality of unit cells, a distance between the intensity center of the unit cell and a nearest intensity center of another unit cell at a perimeter of the unit cell may be at least 0.7 times the height of the unit cell.

Abstract: A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.

Abstract: A method, apparatus, and tangible computer readable medium for processing a Hidden Markov Model (HMM) structure are disclosed herein. For example, the method includes receiving Hidden Markov Model (HMM) information from an external system. The method also includes processing back pointer data and first HMM states scores for one or more NULL states in the HMM information. Second HMM state scores are processed for one or more non-NULL states in the HMM information based on at least one predecessor state. Further, the method includes transferring the second HMM state scores to the external system.

Abstract: A circuit, system, and method for converting self capacitance to a digital value may include a pair of charge transfer circuits, each including a deadband switch network, a sensor capacitor or modulation capacitor, and an integration capacitor may be coupled to a comparator to produce a bitstream representative of the capacitance of the sensor capacitor of one of the charge transfer circuits. The bitstream may be used to indicate a capacitance value of the self capacitance through conversion by a digitizing circuit element.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.

Abstract: A device and method for resisting, non-invasive attacks are disclosed herein. The device includes a random number generator that generates a random number, and a multiplier that multiplies first data and second data in a unit of a bit length determined based on the random number.

Abstract: Techniques for low-power USB Type-C receivers with high DC-level shift tolerance and high noise rejection are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to reject the incoming signal even when the incoming signal includes noise with a magnitude of more than 300 mVpp.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.

Abstract: A radio frequency identification (RFID) integrated circuit includes a transceiver and a processing device. The transceiver may to transmit a first continuous wave radio frequency (RF) signal to a bridge in a no-wire format via an antenna, where the transceiver is to start transmitting the modulated or continuous wave RF signal at a first amplitude value and increase an amplitude of the modulated or continuous wave RF signal to a second amplitude value at which an acknowledge (ACK) pulse is detected. The transceiver may receive a reflected wave RF signal in the no-wire format. The processing device may detect the ACK pulse in the reflected wave RF signal. The processing device may transmit a second modulated or continuous wave RF signal to the transceiver in the no-wire format.

Abstract: A technique for detecting a valley timing at lower cost is described. A drive circuit comprises a peak voltage holder, a valley voltage holder, a center voltage generator, a monitor, and a detector. The peak voltage holder holds a peak voltage of an oscillating signal that is based on a voltage at a terminal of an inductor coupled to a switching element. The valley voltage holder holds a valley voltage of the oscillating signal. The center voltage generator generates a center voltage based on the peak voltage and the valley voltage. The monitor monitors the present value of the voltage at the terminal. The detector detects, as a valley timing, a timing at which a predetermined delay time has elapsed from a timing at which the monitored present value of the voltage at the terminal has fallen below the center voltage.

Abstract: A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

Abstract: Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area.

Abstract: A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.

Abstract: Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, a speech recognition system is provided. The system includes a processing unit configured to divide a received audio signal into consecutive frames having respective frame vectors, an acoustic processing unit (APU), a data bus that couples the processing unit and the APU. The APU includes a local, non-volatile memory that stores a plurality of senones, a memory buffer coupled to the memory, the acoustic processing unit being configured to load at least one Gaussian probability distribution vector stored in the memory into the memory buffer, and a scoring unit configured to simultaneously compare a plurality of dimensions of a Gaussian probability distribution vector loaded into the memory buffer with respective dimensions of a frame vector received from the processing unit and to output a corresponding score to the processing unit.

Abstract: An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

Abstract: An example secure embedded device includes a secure non-volatile memory coupled to a processor. The processor provides a scramble or cipher key and uses a scramble algorithm or a cipher algorithm to scramble or cipher information received from an external device into transformed information. The processor writes a least a portion of the transformed information to a plurality of memory locations of the secure non-volatile memory. The plurality of memory locations is based on the scramble or cipher key.

Abstract: A method for operating a sensing system includes receiving, from a processing device, control information for configuring a capacitance sensing circuit, configuring the capacitance sensing circuit with the control information in response to receiving the control information, and controlling power consumption of the processing device based on the control information and based on a capacitance measured by the capacitance sensing circuit.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.