Abstract: Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device comprises a first region, a second region, a first polysilicon region, and a second polysilicon region. The first polysilicon region is formed over the first and second regions of the semiconductor device. Portions of the first and polysilicon layers that are uncovered by either of a first mask and a second mask are removed. The first mask is formed on the first polysilicon layer and the second mask is formed on the second polysilicon layer in the first region and not on in the second region.

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract: Circuits, systems, and methods for starting up analog devices are provided. One circuit includes an output node at an output voltage (VOUT), a comparator configured to be coupled to a reference voltage (VREF), a feedback loop coupling the output node to the comparator, and a turbo circuit coupled between the output and the output node. The turbo circuit is configured to increase VOUT, the comparator is configured to compare VOUT and VREF, and the turbo circuit is enabled and disabled based on the comparison of VOUT and VREF. One system includes an analog device coupled to the above circuit. A method includes enabling the startup portion to start up the driver portion when VOUT is outside a predetermined voltage of VREF, disabling the startup portion when VOUT is within the predetermined voltage, and enabling the driver portion to drive the analog device subsequent to disabling the startup portion.

Abstract: A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations.

Abstract: Systems, methods, and devices are disclosed for implementing a bootstrapped power circuit. Devices may include a controller configured to generate an output signal. Devices may include a power converter configured to receive the output signal, configured to store an amount of energy in response to receiving the output signal, and further configured to release the amount of energy in response to detecting a change in the output signal. Devices may include a switch configured to be toggled between a first and second position. Devices may include a power source configured to store a second voltage having a second amplitude. Devices may include a bootstrap circuit configured to receive a third voltage from the power source when the switch is in the first position, and configured to receive at least some of the amount of energy from the power converter when the switch is in the second position.

Abstract: A capacitive sensor array comprises large sensor electrodes and small sensor electrodes formed from a single layer of conductive material. Each sensor electrode of a first set of small sensor electrodes is electrically connected to a first pad. A first axis crosses two or more of the sensor electrodes of the first set of small sensor electrodes, and each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the large sensor electrodes from another small sensor electrode of the first set. Each sensor electrode of a second set of small sensor electrodes is electrically connected to a second pad. A second axis crosses two or more of the sensor electrodes of the second set of small sensor electrodes, and each small sensor electrode of the second set is located on an opposite lateral side of one of the large sensor electrodes from another small sensor electrode of the second set.

Abstract: A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint sensor-compatible overlay are also disclosed.

Abstract: A method for downloading information into a secure non-volatile memory of a secure embedded device (SED) during a manufacturing or personalization process. The method involves communicating the information and a software program from a device to a temporary storage memory of the SED. The method also involves starting the software program provided to facilitate an initialization of a first key and to facilitate a transfer of at least a portion of the information from the temporary storage memory to the secure non-volatile memory. In response to starting, the software program, the first key is initialized and the portion of information is transformed into transformed information locally at the SED using at least one of a scramble algorithm and a cipher algorithm. Thereafter, the transformed information is written to a memory element of the secure non-volatile memory.

Abstract: A capacitance sensing circuit receives an application of a power supply. The capacitance sensing circuit controls a switch circuit to connect the power supply to a processing device responsive to the application of the power supply. The capacitance sensing circuit receives, via a control interface and from the processing device, control information to configure the capacitance sensing circuit. The capacitance sensing circuit disconnects the power supply from the processing device subsequent to receiving the control information.

Abstract: An apparatus including a first layer formed from a first conductive material having a first coefficient of thermal expansion and a second layer, coupled to the first layer, the second layer formed from a second conductive material having a second coefficient of thermal expansion, where the second layer is partially filled.

Abstract: A memory including an array of nvSRAM cells and method of operating the same are provided. Each nvSRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including exactly one non-volatile memory (NVM) element, a first transistor coupled to the NVM element through which data true is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM element through which a complement of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM element is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM element, the second transistor is coupled to a second node of the NVM element and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract: Structure of F-RAM cells are described. The F-RAM cell include a contact extending through a first dielectric layer on a surface of a substrate. A barrier structure is formed over the contact by depositing and patterning a barrier layer. A second dielectric layer is deposited over the patterned barrier layer and planarized to expose a top surface of the barrier structure. A ferro-stack is deposited and patterned over the barrier structure to form a ferroelectric capacitor. A bottom electrode of the ferroelectric capacitor is electrically coupled to the diffusion region of the MOS transistor through the barrier structure. The barrier layer is conductive so that a bottom electrode of the ferroelectric capacitor is electrically coupled to the contact through the barrier structure. In one embodiment, patterning barrier layer comprises concurrently forming a local interconnect (LI) on a top surface of the first dielectric layer.

Abstract: Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.

Abstract: An integrated circuit (IC) device can include a plurality of banks, each including a plurality of memory cells, and separately accessible according to a received bank address value, each bank configured to enable accesses on different phases of an internal clock signal; and a plurality of channel groups, each channel group including a plurality of channels, each channel including its own data connections, address connections, and control input connections for accessing the banks, the channels of different groups accessing the memory banks on the different phases of the internal clock signal.

Abstract: A capacitance sensing device can include a reference circuit configured to connect to a reference capacitance, and to generate an electrical reference signal that varies over time according to the reference capacitance and a compare signal; a sense circuit configured to connect to a sense capacitance, and to generate an electrical sense signal that varies over time according to a sense capacitance; a compare circuit having compare inputs coupled to receive the sense signal and the reference signal, and a compare output that provides the compare signal; and a value generation circuit configured to generate an output value corresponding to the compare signal over a predetermined time period.

Abstract: Techniques for fully-differential multi-phase scanning in capacitive fingerprint applications are described herein. In an example embodiment, a system comprises a capacitive fingerprint sensor array and a processing device coupled to the capacitive fingerprint sensor array. The processing device is configured at least to: scan the capacitive fingerprint sensor array in a fully-differential multi-phase mode; receive a plurality of measurements that represents a portion of finger on the capacitive fingerprint sensor array; and generate a fingerprint image for the portion of the finger based on the plurality of measurements. In some embodiments, a capacitive fingerprint sensor array may include receive (RX) electrodes and one or more reference electrodes configured to detect noise, where the one or more reference electrodes have width that is substantially equal to the width of the RX electrodes, but the one or more reference electrodes are disposed at a smaller pitch than the RX electrodes.

Abstract: A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint sensor-compatible overlay are also disclosed.

Abstract: Disclosed is a method for reading from a non-volatile memory (NVM) device including: retrieving a set of data from an NVM array according to a read sequence for a requested set of logical memory locations received from a host device, detecting errors in the set of data, preparing an error indicator to be output to a host device substantially upon detection of the errors and outputting the error indication in response to a command being received from the host device.

Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

Abstract: An apparatus includes a contact grid array disposed on a substrate in a non-orthogonal row-column format with connection elements arranged in a hexagonal configuration. The contact grid array has an orientation based, at least in part, on an area available for the contact grid array on the substrate. A method to determine the orientation of the contact grid array includes identifying the area available for a contact grid array on a substrate and determining the orientation for the contact grid array based, at least in part, on the area available for the contact grid array on the substrate.