Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: A method for operating a read command of N complementary memory cells, the method includes the steps of determining if each of the first and second memory cells of the N complementary memory cells is in a first binary state or a second binary state, generating a count value by counting a total number of the first and second memory cells that are in the first binary state, and determining if the N complementary memory cells are programmed or erased based on a result of comparing the count value to a threshold number.

Abstract: A technique for improving capacitive sensing accuracy. Concurrent activations of multiple capacitance sensors within an array of capacitance sensors are sensed. One of the concurrent activations of the multiple capacitance sensors is accepted as a user activation. Remaining ones of the concurrent activations of the multiple capacitance sensors are rejected based on their physical location within the array of capacitance sensors relative to the one of the concurrent activations of the multiple capacitance sensors accepted as the user activation.

Abstract: A programmable device includes reconfigurable analog circuitry, reconfigurable digital circuitry, a plurality of input/output (I/O) blocks, and a global mapping system. The global mapping system is configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

Abstract: Described herein is a system comprising a peripheral device that is connected to a host device over a bus compatible with USB 3.0. The host device comprises a reduced functionality USB host controller configured to perform a set of one or more preprogrammed functions from the USB 3.0 specification, and a universal asynchronous receiver and transmitter (UART) configured to sample USB response data received from the peripheral device over the bus.

Abstract: A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Abstract: A Universal Serial Bus (USB) Type-C connector subsystem is described herein. An integrated circuit (IC) chip device includes a Universal Serial Bus (USB) Type-C subsystem. The USB Type-C subsystem is to operate an Ra termination circuit that consumes no more than a first predetermined amount of current after the Ra termination circuit is applied to a Vconn line of the Type-C subsystem, or to operate a standby reference circuit in a low power mode of the device to perform detection on a Configuration Channel (CC) line of the Type-C subsystem, where the device consumes no more than a second predetermined amount of current in the low power mode.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: A capacitive sensor array comprises large sensor electrodes and small sensor electrodes formed from a single layer of conductive material. Each sensor electrode of a first set of small sensor electrodes is electrically connected to a first pad. A first axis crosses two or more of the sensor electrodes of the first set of small sensor electrodes, and each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the large sensor electrodes from another small sensor electrode of the first set. Each sensor electrode of a second set of small sensor electrodes is electrically connected to a second pad. A second axis crosses two or more of the sensor electrodes of the second set of small sensor electrodes, and each small sensor electrode of the second set is located on an opposite lateral side of one of the large sensor electrodes from another small sensor electrode of the second set.

Abstract: A fingerprint sensor-compatible overlay material which uses anisotropic conductive material to enable accurate imaging of a fingerprint through an overlay is disclosed. The anisotropic conductive material has increased conductivity in a direction orthogonal to the fingerprint sensor, increasing the capacitive coupling of the fingerprint to the sensor surface, allowing the fingerprint sensor to accurately image the fingerprint through the overlay. Methods for forming a fingerprint sensor-compatible overlay are also disclosed.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: A capacitive sensor array may include a first set of sensor electrodes and a second set of sensor electrodes. Each of the second set of sensor electrodes may intersect each of the first set of sensor electrodes to form a plurality of unit cells each corresponding to a pair of sensor electrodes including one of the first set of sensor electrodes and one of the second set of sensor electrodes. Each point within each of the plurality of unit cells may nearer to a gap between the pair of sensor electrodes corresponding to the unit cell than to a gap between any different pair of sensor electrodes, and a first trace pattern within a first unit cell of the plurality of unit cells may be different from a second trace pattern within an adjacent unit cell of the plurality of unit cells.

Abstract: A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second gate conductor can be formed over a second gate dielectric structure, adjacent to the integrate dielectric structure. A dielectric layer can be formed over the substrate, the first and second gate conductors, and the inter-gate dielectric structure. The first gate conductor may be used to make a memory gate and the second gate conductor can be used to make a select gate of a split-gate memory cell.

Abstract: A memory including an array of nvRAM cells and method of operating the same are provided. Each nvRAM cell includes a volatile charge storage circuit, and a non-volatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.

Abstract: A method and apparatus varying, by interval, a frequency of a drive signal applied to one electrode of each of a plurality of electrode pairs, select a frequency corresponding to the frequency of the drive signal, monitor changes in capacitance of each of the electrode pairs through receive signals at the selected frequency, from the other electrode of each of the plurality of electrode pairs; and determine a position of at least two objects, which are simultaneously on a touch device, according to the monitored capacitance changes.

Abstract: A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.

Abstract: A method and apparatus include a plurality of sensor elements arranged within an integrated circuit package and a controller arranged within the integrated circuit package and coupled to the plurality of sensor elements. The controller is configured to apply a transmit signal to a first sensor element of the plurality of sensor elements and receive a receive signal from a second sensor element of the plurality of sensor elements. The receive signal represents a mutual capacitance of the first sensor element and the second sensor element.

Abstract: A method and apparatus for sensing a conductive object by a mutual capacitance sensing array is described according to an embodiment of the present invention. The mutual capacitance sensing array comprises one or more sensor elements. Each sensor element comprises an outer frame including a conductive material. A cavity is formed within the interior of the outer frame. In an example embodiment, the sensor elements include transmit (TX) sensor elements and receive (RX) sensor elements that are disposed in a stackup that comprises a substrate, where the TX sensor elements are laminated by optically clear adhesive and are disposed on one side of the substrate, and where the RX sensor elements are laminated by optically clear adhesive and are disposed on a different side of the substrate than the TX elements.

Abstract: Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, a speech recognition system is provided. The system includes a processing unit configured to divide a received audio signal into consecutive frames having respective frame vectors, an acoustic processing unit (APU), a data bus that couples the processing unit and the APU. The APU includes a local, non-volatile memory that stores a plurality of senones, a memory buffer coupled to the memory, the acoustic processing unit being configured to load at least one Gaussian probability distribution vector stored in the memory into the memory buffer, and a scoring unit configured to simultaneously compare a plurality of dimensions of a Gaussian probability distribution vector loaded into the memory buffer with respective dimensions of a frame vector received from the processing unit and to output a corresponding score to the processing unit.

Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.