Abstract: A circuit, system, and method for converting mutual capacitance to a digital value is described. Charge packets are transferred from a mutual capacitance to a pair of integration capacitors during alternate charge and discharge cycles. The time required to bring the discharged integration capacitor to the same potential as the charged integration capacitor with a current source is measured as a single-slope analog-to-digital converter (ADC). The output of the ADC is representative of the mutual capacitance.

Abstract: Methods and apparatus include and amplifier circuit and a first capacitor branch including a first plurality of capacitors. The first capacitor branch couples to an input signal and to an input of the amplifier circuit. A second capacitor branch includes a second plurality of capacitors. The second capacitor branch couples to the input of the amplifier circuit and to an output of the amplifier circuit.

Abstract: An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.

Abstract: An example sensor array includes a first electrode disposed in a first layer, multiple second electrodes disposed in a second layer, and multiple third electrodes disposed outside of the first layer. The second electrodes are galvanically isolated from the first electrode and the third electrodes. In a plan view of the fingerprint sensor array, an area of each third electrode is located within an area of the first electrode.

Abstract: A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

Abstract: A semiconductor device that has a split gate charge trapping memory cell having select and memory gates of different heights is presented herein. In an embodiment, the semiconductor device also has a low voltage transistor and a high voltage transistor. In one embodiment, the gates of the transistors are the same height as the select gate. In another embodiment, the gates of the transistors are the same height as the memory gate.

Abstract: A design system is provided. In one embodiment the design system includes an input module to receive specification data for a designed circuit including a configurable integrated circuit (IC). The configurable IC includes a number of analog elements for which parameters can be set by the design system, and a plurality of configurable signal path elements including an analog-to-digital converter (ADC) that is utilized in a plurality of different signal paths. The design system further includes a design module to generate a design for the designed circuit based on the specification data, and an output module to set parameters of at least one of the analog elements based on the design. Other embodiments are also provided.

Abstract: A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component, a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface. The serial peripheral interface (SPI) double data rate (DDR) interface accesses the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and the serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component where data is accessed on leading and falling edges of a clock signal.

Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the memory transistor comprises an oxide-nitride-oxide (ONO) stack on a surface of a semiconductor substrate, and a high work function gate electrode formed over a surface of the ONO stack. Preferably, the gate electrode comprises a doped polysilicon layer, and the ONO stack comprises multi-layer charge storing layer including at least a substantially trap free bottom oxynitride layer and a charge trapping top oxynitride layer. More preferably, the device also includes a metal oxide semiconductor (MOS) logic transistor formed on the same substrate, the logic transistor including a gate oxide and a high work function gate electrode. In certain embodiments, the dopant is a P+ dopant and the memory transistor comprises N-type (NMOS) silicon-oxide-nitride-oxide-silicon (SONOS) transistor while the logic transistor a P-type (PMOS) transistor.

Abstract: A device, system, and method of a programmable circuit configured to operate in a buffered drive mode and blanking mode is disclosed. The programmable circuit includes a continuous-time digital-to-analog converter (CTDAC), a continuous-time block (CTB), coupled to the CTDAC, and a sample and hold (SH) circuit coupled to the CTDAC and the CTB. The programmable circuit is configured to operate in a buffered drive mode to buffer an output signal from the CTDAC. The programmable circuit, in buffered drive mode, is further configured to operate in a blanking mode to cause the SH circuit to perform a blanking operation on the CTDAC output signal.

Abstract: A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one demodulated value for processing by a channel engine. The channel engine may generate a capacitance result value that is based, in part, on the demodulated value and is stored in a memory.

Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

Abstract: A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The switching circuit further includes a gate voltage generating circuit configured to switch voltage applied to the gate of the PLDMOS between a first voltage and a second voltage, wherein the first voltage is substantially the same as an input voltage from the converting circuit, and wherein a difference between the first voltage and the second voltage is lower than the gate-source breakdown voltage of the PLDMOS.

Abstract: According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. An adhesive paste is then applied to attach the semiconductor die to the lead frame such that the adhesive paste fixes the die to a portion of the lead frame. The adhesive paste may be applied directly between die and the lead frame or may be applied in conjunction with a frame tape.

Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction it spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

Abstract: Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric capacitor formed thereon.

Abstract: A temperature detection circuit and a temperature measurement circuit capable of detecting and measuring temperatures precisely are disclosed. The temperature detection circuit includes n temperature detectors (n is an integer of 2 or more), each of the temperature detectors being configured to output a detection signal of high level when a temperature of an object reaches a first value, and a temperature determination part configured to determine whether or not the temperature of the object has reached a second value based on a count of high-level detection signals.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.