Patents Assigned to Cypress Semiconductor
  • Non-Volatile Memory With Silicided Bit Line Contacts
    Publication number: 20170250192
    Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 31, 2017
    Applicant: Cypress Semiconductor Corporation
    Inventors: Ching-Huang LU, Simon S. Chan, Hidehiko Shiraiwa, Lei Xue
  • Detect and differentiate touches from different size conductive objects on a capacitive button
    Patent number: 9746507
    Abstract: Apparatuses and methods of distinguishing between a finger and a stylus proximate to a touch surface are described. One apparatus includes a first circuit to obtain capacitance measurements of sense elements when a conductive object is proximate to a touch surface. The apparatus also includes a second circuit coupled to the first circuit. The second circuit is operable to detect whether the conductive object activates the first sense element, second sense element, or both, in view of the capacitance measurements. To distinguish between a stylus and a finger as the conductive object, the second circuit determines the conductive object as being the stylus when the second sense element is activated and the first sense element is not activated and determines the conductive object as being the finger when the first sense element and the second sense element are activated.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 29, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Vibheesh Bharathan
  • Stochastic signal density modulation for optical transducer control
    Patent number: 9750097
    Abstract: A controller for optical transducers uses stochastic signal density modulation to reduce electromagnetic interference.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 29, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: David Van Ess, Patrick N Prendergast
  • SONOS stack with split nitride memory layer
    Patent number: 9748103
    Abstract: A semiconductor device includes a polysilicon substrate, a first oxide layer formed on the polysilicon substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 29, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
  • Providing a baseline capacitance for a capacitance sensing channel
    Patent number: 9746974
    Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner may generate a baseline current using a baseline capacitor and may provide the baseline current to the channel input.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 29, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Denis Ellis, Roman Ogirko, Kaveh Hosseini, Brendan Lawton, Timothy Williams, Gabriel Rowe
  • Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells
    Patent number: 9747987
    Abstract: Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 29, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Venkatraman Prabhakar, Long T Hinh, Sarath Chandran Puthenthermadam, Kaveh Shakeri
  • Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
    Patent number: 9741803
    Abstract: A charge trap memory device is provided. In one embodiment, the charge trap memory device includes a semiconductor material structure having a vertical channel extending from a first diffusion region formed in a semiconducting material to a second diffusion region formed over the first diffusion region, the vertical channel electrically connecting the first diffusion region to the second diffusion region. A tunnel dielectric layer is disposed on the vertical channel, a multi-layer charge-trapping region including a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer, and a second nitride layer comprising a deuterium-free trap-dense, oxygen-lean nitride disposed on the first nitride layer. The second nitride layer includes a majority of charge traps distributed in the multi-layer charge-trapping region.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 22, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sagy Levy, Fredrick Jenne, Krishnaswamy Ramkumar
  • Multiple phase-shift photomask and semiconductor manufacturing method
    Patent number: 9733574
    Abstract: Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device may be raised or lowered relative to other areas of the semiconductor device. Therefore, focusing the light on one area causes another to become unfocused. By carefully designing a photomask to cause phase shifts of the light transmitted therethrough, focus across all areas of the semiconductor device can be achieved during photolithography, which results in sharp and accurate patterns formed on the semiconductor device.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 15, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gong Chen, Frank Tsai
  • Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock
    Patent number: 9734877
    Abstract: A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate the memory array.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 15, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hamid Khodabandehlou, Syed Babar Raza
  • Pressure detection system for touch-sense devices
    Patent number: 9733745
    Abstract: A touch-sense device includes an overlay, such as a rough overlay or a compliant overlay, on a sensing layer. Use of the overlay changes a response of the sensing layer so that a light press is more distinguishable from a strong press by sensing electronics. Distinguishing the light press from the strong press enables the sensing electronics to report additional information in response to a press. In one example, a sensor signal of the sensing layer attains a first magnitude for a light press, and a second magnitude for a strong press, enabling the strong press to be distinguished. In another example, a sensor signal has a second edge in response to a strong press, and detection of the second edge enables the strong press to be distinguished. In various embodiments, a surface of the overlay has protrusions and/or cavities and/or is compressible.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 15, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Victor Kremin
  • Ion implantation-assisted etch-back process for improving spacer shape and spacer width control
    Patent number: 9735289
    Abstract: Disclosed herein is a semiconductor device including a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion that is substantially perpendicular to the substrate. Further, disclosed herein, are methods associated with the fabrication of the aforementioned semiconductor device.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: August 15, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gong Chen, Scott Bell
  • Method of depositing copper using physical vapor deposition
    Patent number: 9728414
    Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50.degree. C. or less, with the deposition taking place at a power level of 300 W or less.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 8, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Wen Yu, Stephen B. Robie, Jeremias D. Romero
  • Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs
    Patent number: 9727123
    Abstract: Techniques for power Field Effect Transistor (power-FET) gate drivers are described herein. In an example embodiment, a device comprises a Universal Serial Bus (USB) subsystem that is disposed in a monolithic integrated circuit (IC). The USB subsystem comprises a gate-driver circuit configured to selectively control an external N-channel power-FET or an external P-channel power-FET.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 8, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Anup Nayak, Ramakrishna Venigalla
  • Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions
    Publication number: 20170221768
    Abstract: Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and dram regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 3, 2017
    Applicant: Cypress Semiconductor Corporation
    Inventors: Shenqing Fang, Unsoon KIM
  • Data writing method and system
    Patent number: 9721665
    Abstract: A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Tetsuhiro Kodama
  • Integration of a memory transistor into high-k, metal gate CMOS process flow
    Patent number: 9721962
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Reconfigurable circuit having rows of a matrix of registers connected to corresponding ports and a semiconductor integrated circuit
    Patent number: 9720879
    Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shinichi Sutou, Ichiro Kasama, Kyoji Sato, Takashi Hanai, Kiyomitsu Katou, Takahiro Kubota, Junji Sahoda
  • System and method for controlling a target device
    Patent number: 9720805
    Abstract: Target device monitoring systems and methods are presented. In one embodiment, a host emulation target device control method includes receiving high level express interface direction to change a design element value. The design element values are associated with an operating target device. Design element values corresponding to the direction are created. The design element values are also forwarded to the operating target device in real time.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kenneth Ogami, Andrew Best, Marat Zhaksilikov
  • Bus sharing scheme
    Patent number: 9720865
    Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: August 1, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy J. Williams, David G. Wright, Harold Kutz, Eashwar Thiagarajan, Warren S. Snyder, Mark E Hastings
  • Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
    Patent number: 9716153
    Abstract: Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: July 25, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sagy Levy, Fredrick Jenne, Krishnaswamy Ramkumar