Abstract: A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first chip; exposing at least a portion of an electrical contact electrically coupled to a component in the first chip by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

Abstract: A Universal Serial Bus (USB) Type-C connector subsystem is described herein. An integrated circuit (IC) chip device includes a Universal Serial Bus (USB) Type-C subsystem. The USB Type-C subsystem is to operate an Ra termination circuit that consumes no more than a first predetermined amount of current after the Ra termination circuit is applied to a Vconn line of the Type-C subsystem, or to operate a standby reference circuit in a low power mode of the device to perform detection on a Configuration Channel (CC) line of the Type-C subsystem, where the device consumes no more than a second predetermined amount of current in the low power mode.

Abstract: A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.

Abstract: Embodiments include a method, apparatus, and computer program product for authentication for speech recognition. The method can include sensing an authentication device with a target device. One or more decoded voice commands can be processed after verification of the authentication device by the target device. Further, one or more decoded voice commands can be executed by the target device.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and a second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: A charge-trapping NOR (CT-NOR) memory device and methods of fabricating a CT-NOR memory device utilizing silicon-rich nitride (SiRN) in a charge-trapping (CT) layer of the CT-NOR memory device.

Abstract: Described herein are a protecting circuit and an integrated circuit capable of discharging electric current sufficient for an input voltage having a large time variation while suppressing power consumption. The protecting circuit includes: a first shunt circuit including a first shunt pathway connected to an input terminal, the first shunt circuit being configured to have a relatively low discharge capacity of the first shunt pathway and a relatively long response time; a second shunt circuit including a second shunt pathway connected to the input terminal, the second shunt circuit being configured to have a relatively high discharge capacity of the second shunt pathway and a relatively short response time; and a control circuit configured to enable the second shunt pathway to discharge based on a time variation of an input voltage at the input terminal.

Abstract: A method and apparatus scan a first capacitive sensor element that is located in a first scan region for a presence of a conductive object and then scan a second capacitive sensor element that is located in a second scan region for the presence of the conductive object. The scan of the first capacitive sensor element includes applying a ground voltage to a ground element through the second capacitive sensor element, the ground element located in the first scan region.

Abstract: An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

Abstract: Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture. If the read data strobe signal is not received before expiration of a predetermined maximum latency time, the peripheral controller is indicating a read data error back to the host.

Abstract: A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.

Abstract: Multi-bit non-volatile random access memory cells are disclosed. A multi-bit non-volatile random access memory cell may include a volatile storage element and a non-volatile storage circuit. The non-volatile storage circuit may include at least one first pass transistor connected to a data true (DT) node of the volatile storage element and at least one second pass transistor connected to a data complement (DC) node of the volatile storage element. The non-volatile storage circuit may also include multiple non-volatile storage elements. Each non-volatile storage element may be configured to be selectively connectable to the DT node of the volatile storage element via the at least one first pass transistor and selectively connectable to the DC node of the volatile storage element via the at least one second pass transistor, allowing the multi-bit non-volatile random access memory cell to store/recall more than one databit per cell.

Abstract: Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals.

Abstract: Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

Abstract: Apparatuses and methods of sense arrays with non-uniform patterns are described. One capacitive-sense array includes a first set of electrodes and a second set of electrodes. The first set of electrodes intersect the second set of electrodes to form a unit cells each corresponding to an intersection of a pair of electrodes comprising one electrode from the first set and one electrode from the second set. At one of the second set of electrodes includes a non-uniform conductive pattern including a first region being located at the intersection of the respective unit cell and a distal region being at a location within the respective unit cell that is farther away from the intersection than the first region. The first region includes a first conductive surface area and the distal region includes a second conductive surface area that is greater than the first conductive surface area.

Abstract: An encapsulated ferroelectric capacitor or ferroelectric memory cell includes encapsulation materials adjacent to a ferroelectric capacitor, a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and an FEO encapsulation layer over the ferroelectric oxide to provide protection from hydrogen induced degradation.

Abstract: A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.

Abstract: A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.