Patents Assigned to Cypress Semiconductor
  • Multi-standard compliant USB battery charging scheme with detection of host disconnection in ACA-DOCK mode
    Patent number: 9590441
    Abstract: Techniques for controlling the charging of portable devices are described herein. In an example embodiment, an apparatus comprises a controller coupled to a Universal Serial Bus (USB) port that is configured as a dedicated charging port (DCP). The controller is configured to detect whether a battery-charging (BC) compliant device or a BC non-compliant device is attached to the USB port. When a BC compliant device is detected, the controller controls the charging of the BC compliant device (e.g., by providing a maximum of 1.5 A of charging current). When a BC non-compliant device is detected, the controller controls the charging of the BC non-compliant device by providing a higher (e.g., up to 2.4 A) charging current.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 7, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Pradeep Kumar Bajpai, Sanjeev Dwarakanath, Jitendra Ramkrishna Kulkarni, Rishi Agarwal
  • Interrupt latency reduction
    Patent number: 9588916
    Abstract: A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 7, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: David G. Wright
  • Use disposable gate cap to form transistors, and split gate charge trapping memory cells
    Patent number: 9590079
    Abstract: A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: March 7, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Mark Ramsbey, Shenqing Fang
  • Capacitive sensing button on chip
    Patent number: 9588626
    Abstract: A method and apparatus include a plurality of sensor elements arranged within an integrated circuit package and a controller arranged within the integrated circuit package and coupled to the plurality of sensor elements. The controller is configured to apply a transmit signal to a first sensor element of the plurality of sensor elements and receive a receive signal from a second sensor element of the plurality of sensor elements. The receive signal represents a mutual capacitance of the first sensor element and the second sensor element.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 7, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Rajagopal Narayanasamy, Mahadevan Krishnamurthy Narayana Swamy, David G. Wright, Steve Kolokowsky
  • Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses
    Patent number: 9588881
    Abstract: A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of instructions enabling a multitude of possible applications to be supported with a program execution time that is not too long.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 7, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Franck Fillere
  • Configurable capacitor arrays and switched capacitor circuits
    Patent number: 9590592
    Abstract: A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one demodulated value for processing by a channel engine. The channel engine may generate a capacitance result value that is based, in part, on the demodulated value and is stored in a memory.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 7, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jaskarn Singh Johal, Erhan Hancioglu, Renee Leong, Harold M. Kutz, Eashwar Thiagarajan, Onur Ozbek
  • Split-gate semiconductor device with L-shaped gate
    Patent number: 9589805
    Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: March 7, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Scott Bell, Chun Chen, Lei Xue, Shenqing Fang, Angela T. Hui
  • Memory access bases on erase cycle time
    Patent number: 9588695
    Abstract: Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for improving a read margin in non-volatile semiconductor memory device. An embodiment includes measuring an erase-time of a memory block in a memory device and associating an indicator from the plurality of indicators for the memory block. The indicator is saved and later retrieved during a read operation.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 7, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Mee-Choo Ong, Wei-Kent Ong, Ogiwara Yuusuke, Sie-Wei Henry Lau
  • Control apparatus, and control method for buck-boost power supply with two primary switches
    Patent number: 9590508
    Abstract: A control apparatus, a buck-boost power supply, and a control method that can control an output part comprising two primary switches which are N-type transistors without changing the switching frequency are provided.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: March 7, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Makoto Yashiki, Toru Miyamae
  • Simultaneous formation of a top oxide layer in a silicon-oxide-nitride-oxide-silicon (SONOS) transistor and a gate oxide in a metal oxide semiconductor (MOS)
    Patent number: 9583501
    Abstract: A semiconductor chip includes a base of a memory transistor in a first region of a substrate, and a base of a metal oxide semiconductor (MOS) transistor in a second region of the substrate. The base of the memory transistor includes a channel in a surface of substrate, a tunnel layer over the channel, and a nitride layer over the tunnel layer. The base of the MOS transistor includes a channel in the surface of substrate. The MOS transistor is coupled to the memory transistor through a shared diffusion region formed in the surface of substrate between the channel of the MOS transistor and the channel of the memory transistor. A plasma oxide overlying the nitride layer and the surface of the substrate to form a top oxide layer over the nitride layer and a gate oxide layer over the surface of substrate in the second region.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: February 28, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Jeong-Mo Hwang
  • Memory devices and methods having multiple address accesses in same cycle
    Patent number: 9576630
    Abstract: A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: February 21, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Dinesh Maheshwari
  • Control circuit
    Patent number: 9578699
    Abstract: Provided is a control circuit capable of suppressing flickering of an LED while preventing degradation of the power efficiency. A control circuit is configured to control electric power to an LED illumination based on a rectified drive voltage, the rectified drive voltage being a drive signal rectified by a rectifier, the drive signal being an AC signal whose phase is controlled by a dimmer including a switching device. The control circuit includes a time period detection part configured to detect a time period in which a voltage value of the rectified drive voltage is less than or equal to a predetermined value; and a dimmer current control part configured so that a control current to the dimmer is greater than or equal to a holding current of the switching device during the time period detected.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: February 21, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: Kazunori Nishizono
  • Reducing sleep current in a capacitance sensing system
    Patent number: 9575606
    Abstract: An apparatus and method of measuring a collective capacitance on a group of capacitive sense elements from at least one of rows or columns of a capacitance sense array when in a first mode, and individually measuring capacitances on each of the rows and columns when in a second mode.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: February 21, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventor: David G. Wright
  • Analog-digital converter and control method
    Patent number: 9577654
    Abstract: In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: February 21, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masashi Kijima, Satoru Mizuta, Tsutomu Tanii, Hiroyuki Matsunami
  • Development, programming, and debugging environment
    Patent number: 9575748
    Abstract: A method includes receiving hardware description code that generically describes circuitry, and translating the hardware description code into one or more configuration files specific to a programmable system. The method further includes generating program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configuring the programmable system to implement the circuitry according to the configuration files and the program code.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: February 21, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Haneef Mohammed, Jack Griffin
  • TAPE CHIP ON LEAD USING PASTE DIE ATTACH MATERIAL
    Publication number: 20170047272
    Abstract: According to various embodiments, systems and methods for packaging a semiconductor device are provided. The disclosure discusses a semiconductor die having a top side and a bottom side that is disposed on a lead frame. An adhesive paste is then applied to attach the semiconductor die to the lead frame such that the adhesive paste fixes the die to a portion of the lead frame. The adhesive paste may be applied directly between die and the lead frame or may be applied in conjunction with a frame tape.
    Type: Application
    Filed: December 16, 2015
    Publication date: February 16, 2017
    Applicant: Cypress Semiconductor Corporation
    Inventors: Lai Nguk CHIN, Paphat PHAOHARUHAN, Sally FOONG
  • High reliability non-volatile static random access memory devices, methods and systems
    Patent number: 9570152
    Abstract: A memory cell includes a storage element coupled to a first data node and a second data node, a first programmable nonvolatile element and a second programmable nonvolatile element, a first switch element and a second switch element. The first switch element is configured to couple the first programmable nonvolatile element to the first data node during a first read mode of the memory cell. The second switch element is configured to couple the second programmable nonvolatile element to the second data node during the first read mode.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: February 14, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Suhail Zain, Walt Anderson, Helmut Puchner, David W. Still
  • Gate fringing effect based channel formation for semiconductor device
    Patent number: 9570458
    Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 14, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
  • Apparatus and method for rounded ONO formation in a flash memory device
    Patent number: 9564331
    Abstract: A method and apparatus for continuously rounded charge trapping layer formation in a flash memory device. The memory device includes a semiconductor layer, including a source/drain region. An isolation region is disposed adjacent to the source/drain region. A first insulator is disposed above the source/drain region. A charge trapping layer is disposed within the first insulator, wherein the charge trapping layer comprises a bulk portion and a first tip and a second tip on either side of said bulk portion, wherein said charge trapping layer extends beyond the width of the source/drain region. A second insulator is disposed above the charge trapping layer. A polysilicon gate structure is disposed above the second insulator, wherein a width of said control gate is wider than the width of said source/drain region.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: February 7, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Shenqing Fang, Tung-Sheng Chen, Tim Thurgate, Di Li
  • Body position sensing for equipment
    Patent number: 9564062
    Abstract: A device that includes a receiving surface for positioning at least one human body part, multiple capacitive sensor elements disposed within multiple positioning areas on the receiving surface, a sense circuit configured to compare the capacitance measurements of the sensor elements with threshold capacitance values and generate a signal when the capacitance measurements indicate proximity of a human body part on a positioning area, and an indicator configured to generate a notification when the position of the human body part corresponds with at least one location on the receiving surface.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 7, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Yuanyuan Qin, Hua Liu