Abstract: Structure and method of fabrication of F-RAM cells are described. The F-RAM cell include ferroelectric capacitors forming over and with a pre-patterned barrier structure which has a planarized/chemically and/or mechanically polished top surface. The pre-patterned barrier structure includes multiple oxygen barriers having a structure of a bottom electrode layer over an oxygen barrier layer. The bottom electrode layer forms at least a part of the bottom electrode of the ferroelectric capacitor formed thereon.

Abstract: An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in which the second signal component is temperature dependent.

Abstract: One embodiment includes an I/O bus including a signal line coupled to a signal source and multiple line switches, each line switch to couple a corresponding I/O port to the signal line. Switch logic coupled to the I/O bus may programmatically switch the multiple line switches to couple at least one of the signal source and measurement circuitry to the respective I/O port.

Abstract: Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated by the second modulator based on a second analog signal. The processing logic may be further configured to generate a third bit stream based on a combination of the first bit stream with the second bit stream. The devices may also include second processing logic configured to generate an output signal based on one or more values of the third bit stream. The output signal may characterize a measurement of electrical power associated with an electrical circuit.

Abstract: A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film.

Abstract: Embodiments of the present invention include an acoustic processing device and a method for traversing a Hidden Markov Model (HMM). The acoustic processing device can include a senone scoring unit (SSU), a memory device, a HMM module, and an interface module. The SSU is configured to receive feature vectors from an external computing device and to calculate senones. The memory device is configured to store the senone scores and HMM information, where the HMM information includes HMM IDs and HMM state scores. The HMM module is configured to traverse the HMM based on the senone scores and the HMM information. Further, the interface module is configured to transfer one or more HMM scoring requests from the external computing device to the HMM module and to transfer the HMM state scores to the external computing device.

Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.

Abstract: A technique for operating a capacitive sensor array. The technique includes logically grouping capacitance sensors of an array of capacitance sensors into sensor groups. The sensor groups each include at least two capacitance sensors of the array of capacitance sensors. Values indicative of a capacitance for each of the sensor groups are measured. The measured values are then analyzed to determine a location of a user interaction with the array of capacitance sensors.

Abstract: An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target.

Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.

Abstract: A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.

Abstract: A method and apparatus determine a plurality of regions, each of the plurality of regions having a detected change in capacitance value that meets or exceeds a threshold value. In an embodiment, the method and apparatus fit a shape to the plurality of regions and determine another region, the other region being within the fitted shape and not having the detected change in capacitance value that meets or exceeds the threshold value. The method and apparatus may assign an assigned change in capacitance value to the other region.

Abstract: An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output s terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.

Abstract: Methods of fabricating a memory device are described. Generally, the method begins with forming a tunnel dielectric layer over a channel region formed from a silicon containing layer over a surface of a substrate. A first oxygen-rich nitride layer of a multi-layer charge-trapping region is formed on a surface of the tunnel dielectric layer, and a second oxygen-lean nitride layer formed over the first nitride layer. A blocking dielectric layer is formed over a surface of the second layer of the multi-layer charge-trapping region, and a high work function gate electrode upon over the blocking dielectric layer. Other embodiments are also described.

Abstract: A first capacitor and a second capacitor are charged until voltage at the second capacitor settles to a settling voltage. While charging, the first capacitor is alternately switched between a current source and ground. When the settling voltage is reached, charging of the first capacitor is halted. The second capacitor continues to be charged until voltage at the second capacitor reaches a reference voltage. The amount of time it takes for the settling voltage to reach the reference voltage corresponds to a measure of capacitance on the first capacitor.

Abstract: Disclosed herein are systems, methods, and devices for power and energy metering. Devices may include first processing logic coupled to an isolator and configured to receive a first bit stream from a first modulator via the isolator. The first bit stream may be generated by the first modulator based on a first analog signal. The first processing logic may be further configured to receive a second bit stream from a second modulator via the isolator. The second bit stream may be generated by the second modulator based on a second analog signal. The processing logic may be further configured to generate a third bit stream based on a combination of the first bit stream with the second bit stream. The devices may also include second processing logic configured to generate an output signal based on one or more values of the third bit stream. The output signal may characterize a measurement of electrical power associated with an electrical circuit.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: Various embodiments provide for topography aware optical proximity correction that can improve depth of focus during wafer lithography. The system can determine the topography of the wafer using real process information. The topographical variations can be based on random defects or structural details. The system can divide the wafer into regions based on the topography of the regions and determine depth of focus values for each of the regions. Optical proximity correction can then be performed on each region separately, using the separate defocus values to yield an accurate, topographically aware optical proximity correction model for the wafer. For regions with varying topography, optical proximity correction can be performed for two defocus values corresponding to the high and low extremes, such that the resulting simulated contour is satisfies a predetermined criterion associated with accuracy.

Abstract: A method and apparatus to evenly distribute gas over a wafer in batch processing. Several techniques are disclosed, such as, but not limited to, angling an injector to distribute gas towards a proximate edge of the wafer, and/or reducing the amount of overlap in the center of the wafer of gas from subsequent gas injections.

Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a memory array that stores data units as storage locations and burst access circuitry that sequentially accesses N relates storage locations within the memory array, where N>1; and a second IC portion comprising a plurality of burst access registers coupled to the burst access circuitry, each burst access register having register locations to store at least N data units, and being coupled to a corresponding port by a single data unit access path.