Patents Assigned to Cypress Semiconductor
  • Patent number: 9490804
    Abstract: A capacitance sense device can include a plurality of sense electrodes; a nonconductive structure comprising first regions formed over the sense electrodes and second regions formed between first regions that are less compressible than the first regions; a conductive touch surface formed over the nonconductive structure; and a capacitance sense circuit coupled to at least the sense electrodes.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 8, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Shruti Hanumanthaiah, Kannan Srinivasagam
  • Patent number: 9490261
    Abstract: A nitride read only memory (NROM) array includes a silicon substrate having trenches therein, a plurality of polysilicon bit lines deposited in the trenches and connecting columns of memory cells, a layer of (oxide nitride oxide) ONO at least within the memory cells and a plurality of polysilicon word lines to connect rows of the memory cells. An NROM array with a virtual ground architecture includes a plurality of bit lines to connect columns of NROM memory cells, a layer of ONO at least within the memory cells and a plurality of word lines to connect rows of the NROM memory cells, wherein a distance between word lines is at least twice the width of the word lines.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: November 8, 2016
    Assignee: Cypress Semiconductor Ltd.
    Inventors: Ilan Bloom, Amichai Givant, Boaz Eitan
  • Patent number: 9490126
    Abstract: An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device—P-I-N diode structures.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: November 8, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Seungmoo Choi, Sameer Haddad
  • Patent number: 9479171
    Abstract: Disclosed is an integrated circuit voltage level shifter including: a first set of pull-up transistors to selectively pull an output voltage towards a high voltage source level based on an input; a second set of pull-down transistors adapted to selectively pull the output voltage towards a lower voltage source level based on the input and a third set of transistors to limit current flow through the second set of pull-down transistors and to mitigate snapback of the second set of pull-down transistors using a bias gate voltage.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 25, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Roni Varkony, Yoram Betser
  • Patent number: 9472947
    Abstract: A protecting circuit includes: a discharge switch configured to connect to a first terminal and a second terminal; a trigger circuit comprising load devices configured to be connected in series between the first terminal and the second terminal, each of the load devices being configured to consume power; and a shunt circuit comprising, between the trigger circuit and the first terminal or the second terminal, at least one shunt pathway configured to be capable of bypassing at least one of the load devices. The trigger circuit is configured to turn on the discharge switch when a voltage between the first terminal and the second terminal is higher than a first voltage value, and the shunt circuit is configured to electrically connect the shunt pathway when the voltage is higher than a second voltage value that is greater than the first voltage value.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 18, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Takashi Namizaki
  • Patent number: 9472564
    Abstract: The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 18, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Yukio Hayakawa
  • Patent number: 9473144
    Abstract: An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: October 18, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Eashwar Thiagarajan, Harold M. Kutz, Hans Klein, Jaskarn Singh Johal, Jean-Paul Vanitegem, Kendall V. Castor-Perry, Mark E. Hastings, Amsby D. Richardson, Jr., Anasuya Pai Maroor, Ata Khan, Dennis R. Seguine, Onur Ozbek, Carl Ferdinand Liepold
  • Patent number: 9472511
    Abstract: An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: October 18, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sungkwon Lee, Roger Bettman, Sai Prashanth Dhanraj, Dung Ho, Leo F Luquette, Jr., Iman Rezanezhad Gatabi, Andrew Walker
  • Patent number: 9472563
    Abstract: A semiconductor device includes bit lines (12) that are provided in a semiconductor substrate (10) an ONO film (14) that is provided on the semiconductor substrate; word lines that are provided on the ONO film (14) and extend in a width direction of the bit lines (12); and a dummy layer (44) that extends in the width direction of the bit lines (12) and is provided in a bit-line contact region (40) having contact holes formed to connect the bit lines (12) with wiring layers (34). In accordance with the present invention, the proximity effect at the time of word line formation can be restrained, and the variation in the widths of the word lines can be made smaller, or current leakage between the bit lines and the semiconductor substrate can be restrained.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: October 18, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventor: Masatomi Okanishi
  • Patent number: 9466489
    Abstract: A process for forming tilted edge wordline implants is disclosed. The process includes forming a first drain implant in a substrate, forming a first tilted implant in a substrate adjacent a first edge wordline to supplement said first drain implant where the first tilted implant is provided at a tilt angle from a first direction and forming a second tilted implant in the substrate adjacent a second edge wordline to supplement another first drain implant where the second tilted implant is provided at a tilt angle from a second direction. A second drain implant is formed in the substrate.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: October 11, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Tim Thurgate, Yu Sun, Chun Chen
  • Patent number: 9466374
    Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: October 11, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Xiaojun Yu, Venkatraman Prabhakar, Igor G. Kouznetsov, Long T Hinh, Bo Jin
  • Patent number: 9463692
    Abstract: In the display of an image including a fixed background image and a variation image of the background image, at least one of the amount of data to be held and the amount of work to be processed is reduced. A display control device acquires pixel description data including a combination of position information for specifying a position on a pixel array and address information for specifying an address in an image storage unit of image data which is displayed at the position specified by the position information. Furthermore, the display control device reads out the image data from the address of the image storage unit specified by the address information and specifies the position on the pixel array specified by the image description data to the display to input the read out image data.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 11, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Minoru Usui
  • Patent number: 9465576
    Abstract: A first-in-first-out (FIFO) memory device may include a plurality of memory locations configurable into M input queues comprising sequences of input data values and N output queues for storing sequences of output data values, wherein N is not equal to M.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: October 11, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Dinesh Maheshwari
  • Patent number: 9466496
    Abstract: Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: October 11, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Angela Tai Hui, Scott Bell, Shenqing Fang
  • Patent number: 9461247
    Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is then formed on the layer.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: October 4, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Matthew Buynoski, Seungmoo Choi, Chakravarthy Gopalan, Dongxiang Liao, Christie Marrian
  • Patent number: 9460974
    Abstract: A method of making a semiconductor structure is provided. The method includes forming a tunneling layer overlying a first channel connecting a source and a drain. A charge storage layer is formed overlying the tunneling layer, the charge storage layer comprises forming a substantially trap free first layer over the tunneling layer, and forming a trap dense second layer over the first layer. Finally, a blocking structure is formed on the charge storage layer by plasma oxidation. A thickness of the charge storage layer is reduced through oxidation of a portion of the charge storage layer during the formation of the blocking structure. Other embodiments are also described.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 4, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jeong Soo Byun, Krishnaswamy Ramkumar
  • Patent number: 9461562
    Abstract: An apparatus includes a voltage monitoring device to generate a brownout indication signal in response to a change in a power supply voltage. The apparatus also includes a mode control device to control a temporal response of the voltage monitoring device to the change in the power supply voltage based, at least in part, on a voltage level of the power supply voltage.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: October 4, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Jaskarn Singh Johal, Andrew C. Page, Timothy John Williams
  • Patent number: 9459842
    Abstract: In one embodiment, a method for supporting multivariable functions of an application includes receiving user input pertaining to two or more variables associated with a multivariable function of the application, and then causing code for the function to be automatically generated to update the variables based on the user input.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 4, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kenneth Y. Ogami, Doug Anderson, Andrew Best
  • Patent number: 9455027
    Abstract: An integrated circuit (IC) device can include a memory array section comprising a plurality of memory arrays that each include memory cells for storing data values; a data path section having switching circuits configured to enable data paths between the memory arrays and a plurality of input/outputs (I/Os) of the IC device; and a power fill control circuit configured to activate power-fill circuits in the IC device to perform non-mission mode operations that consume current, the amount of non-mission mode operations varying in response to mission mode circuit activity in the IC device; wherein mission mode circuit activity includes circuit activity resulting from a user input to the IC device.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 27, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Derwin W. Mattos, Thinh Tran
  • Patent number: 9455352
    Abstract: Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: September 27, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan Choi, Angela Hui