Patents Assigned to Cypress Semiconductor
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Patent number: 9368644Abstract: Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate. The gate structure includes a charge trapping dielectric formed between the substrate and a first poly layer. A top dielectric is formed over the poly layer and a sidewall dielectric is formed on a side of the poly layer. A second poly layer is formed over the gate structure such that a portion of the second poly layer includes a vertical portion that is in contact with the sidewall dielectric and a top portion that is in contact with the top dielectric. The top portion of the second poly layer can then be removed through, for instance, planarization.Type: GrantFiled: December 20, 2013Date of Patent: June 14, 2016Assignee: Cypress Semiconductor CorporationInventors: Shenqing Fang, Chun Chen, David Matsumoto, Mark Ramsbey
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Patent number: 9368393Abstract: A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.Type: GrantFiled: October 17, 2014Date of Patent: June 14, 2016Assignee: Cypress Semiconductor CorporationInventor: Calvin T. Gabriel
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Patent number: 9368424Abstract: A method of fabricating a semiconductor device includes the steps of providing a heat-resistant sheet on an interposer so as to cover electrode terminals provided on the interposer, and sealing a semiconductor chip on the interposer sandwiched between molds with a sealing material. The electrode terminals are covered by the heat-resistant resin for protection, and the semiconductor chip is then sealed with resin. It is thus possible to avoid the problem in which contaminations adhere to the electrode terminals. This makes it possible to prevent the occurrence of resin burrs on the interposer and contamination of the electrode pads and to improve the production yield.Type: GrantFiled: May 20, 2005Date of Patent: June 14, 2016Assignee: Cypress Semiconductor CorporationInventors: Yasuhiro Shinma, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Junji Tanaka
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Patent number: 9362293Abstract: Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines.Type: GrantFiled: December 20, 2013Date of Patent: June 7, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Hagop Nazarian, Richard Fastow, Lei Xue
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Patent number: 9361994Abstract: A memory structure is provided including an array of non-volatile memory (NVM) cells arranged in rows and columns, each cell including a NVM transistor having a body bias terminal coupled to body bias supply. The memory structure further includes a control system to control the body bias supply to adjust a body bias voltage coupled to the body bias terminals during read operations of the memory structure to compensate for shifts in threshold voltages (VTH) of the NVM transistors to maintain a read current window (IRCW) between a cell in which the NVM transistor is ON and a sum of leakage current through cells in which the NVM transistor is OFF. Methods of operating the memory structure are also described.Type: GrantFiled: June 15, 2015Date of Patent: June 7, 2016Assignee: Cypress Semiconductor CorporationInventor: Igor Kouznetsov
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Patent number: 9361973Abstract: An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal; and a controller subsystem configured to control accesses between the channels and the memory banks, including up to an access on every channel on consecutive cycles of the clock signal.Type: GrantFiled: March 28, 2014Date of Patent: June 7, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventor: Dinesh Maheshwari
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Patent number: 9360972Abstract: An example apparatus includes a sensing area including a sensor matrix, a first conductor and a second conductor. The first conductor is coupled to a first sensor of the sensor matrix and is configured to be coupled to a sensing module. The second conductor is coupled to a second sensor of the sensor matrix and is configured to be coupled to the sensing module. In embodiments, the first sensor consumes a first area, the second sensor and a length of the first conductor reside within a second area that is smaller than or equal to the first area consumed by the first sensor, and the length of the first conductor is routed between an edge of the sensing area and the second sensor.Type: GrantFiled: March 13, 2013Date of Patent: June 7, 2016Assignee: Cypress Semiconductor CorporationInventors: Benjamin James Avery, Cole D. Wilson, Jonathan R. Peterson
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Patent number: 9360968Abstract: We describe an apparatus including a plurality of sensing elements, a conductive layer, and a compressive layer interposed between the plurality of sensing elements and the conductive layer. The conductive layer can include a plurality of segments. A user applies a force to an actuator positioned over the conductive layer. The actuator changes a capacitance of at least one capacitor formed by at least one of the plurality of sensing elements, the conductive layer (at least one segment), and the compressive layer by reducing the distance between the at least one of the plurality of sensing elements and the conductive layer responsive to the applied force. The device measures and calculates a magnitude and direction of the force by measuring the change in the capacitance.Type: GrantFiled: February 22, 2008Date of Patent: June 7, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventor: David Wright
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Patent number: 9362287Abstract: A semiconductor device includes: a first transistor and a second transistor disposed in or on a silicon substrate; an element isolation structure that isolates the first transistor and the second transistor, the element isolation structure comprising at least one of a first element isolation film disposed in a region of a first well disposed in a formation area of the first transistor, or a second element isolation film disposed in a region of a second well disposed in a formation area of the second transistor, and a third well disposed under the first well in the silicon substrate and is electrically connected to the second well. The first element isolation film or the second element isolation film has a portion that does not extend over a boundary between the first well and the second well.Type: GrantFiled: November 12, 2014Date of Patent: June 7, 2016Assignee: Cypress Semiconductor CorporationInventor: Akira Eguchi
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Publication number: 20160154507Abstract: Disclosed herein are systems, methods, and devices for touch event and hover event detection. Devices as disclosed herein may include a first electrode implemented in a capacitive sensor. The devices may also include a second electrode implemented in the capacitive sensor. The devices may further include a controller coupled to the first electrode and the second electrode, where the controller is configured to determine whether a touch event or a hover event has occurred based on a first self-capacitance measurement of the first electrode, a second self-capacitance measurement of the second electrode, and a mutual capacitance measurement of the first electrode and the second electrode.Type: ApplicationFiled: May 15, 2015Publication date: June 2, 2016Applicant: Cypress Semiconductor CorporationInventors: Vibheesh Bharathan, Peter G. Vavaroutsos, Jinghui Mu
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Patent number: 9355051Abstract: A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.Type: GrantFiled: September 10, 2010Date of Patent: May 31, 2016Assignee: Cypress Semiconductor CorporationInventor: Clifford Alan Zitlaw
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Patent number: 9355849Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.Type: GrantFiled: June 13, 2013Date of Patent: May 31, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick B. Jenne, Sam G. Geha
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Patent number: 9354272Abstract: The automatic loading and unloading of devices for burn-in testing is facilitated by loading burn-in boards in a magazine with the stacked boards in the magazine moved into and out of a burn-in oven by means of a trolley. The trolley can include an elevator whereby a plurality of magazines can be stacked in the oven for the simultaneous burn-in testing of devices mounted on the burn-in boards. Each board has rollers on one end which are engagable by pneumatically actuated cam mechanisms for inserting the board into an electrical contact in the oven for burn-in tests. Preferably, the cam mechanisms allow for extraction of a single board for inspection.Type: GrantFiled: June 29, 2012Date of Patent: May 31, 2016Assignee: Cypress Semiconductor CorporationInventors: Wan Yen Teoh, Paiboon Subpanyadee, Kurt Joseph Perez, Chai Soon Teo, Swee Hin Ong
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Patent number: 9355725Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.Type: GrantFiled: December 11, 2014Date of Patent: May 31, 2016Assignee: Cypress Semiconductor CorporationInventors: Bo Jin, Krishnaswamy Ramkumar, Xiaojun Yu, Igor Kouznetsov, Venkatraman Prabhakar
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Patent number: 9356035Abstract: A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently.Type: GrantFiled: August 4, 2014Date of Patent: May 31, 2016Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor G. Kouznetsov, Venkatraman Prabhakar
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Patent number: 9349877Abstract: A nonvolatile trapped-charge memory device and method of fabricating the same are described. Generally, the memory device includes a tunneling layer on a substrate, a charge trapping layer on the tunneling layer, and a blocking layer on the charge trapping layer. The tunneling layer includes a nitrided oxide film formed by annealling an oxide grown on the substrate using a nitrogen source. The tunneling layer comprises a first region proximate to the substrate, and a second region proximate to the charge trapping layer, and wherein the nitrogen concentration decreases from a first interface between the second region and the charge trapping layer to a second interface between the first region and the substrate to reduce nitrogen trap density at the second interface. Other embodiments are also described.Type: GrantFiled: January 28, 2014Date of Patent: May 24, 2016Assignee: Cypress Semiconductor CorporationInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Frederick B. Jenne
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Patent number: 9349824Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising an oxygen-rich oxynitride overlying the tunneling layer, and a second charge storing layer overlying the first charge storing layer comprising a silicon-rich and nitrogen-rich oxynitride layer that is oxygen-lean relative to the first charge storing layer and comprises a majority of charge traps distributed in the multi-layer charge storing layer; and forming a blocking layer on the second oxynitride layer; and forming a gate layer on the blocking layer. Other embodiments are also described.Type: GrantFiled: February 4, 2014Date of Patent: May 24, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Frederick B. Jenne, Sam G Geha
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Patent number: 9343470Abstract: A polysilicon gate electrode is formed in a memory cell area, and a dummy polysilicon gate electrode is formed in a logic cell area of a silicon substrate. The dummy polysilicon gate electrode is removed and a gate insulation film and a metal gate electrode having a recess portion are formed. Further, contact holes are formed on source regions and drain regions of the memory cell area and the logic cell area. The recess portion of the metal gate electrode and the contact holes are filled with a wiring metal, substantially simultaneously, and thereafter the wiring metal is planarized by polishing.Type: GrantFiled: August 13, 2014Date of Patent: May 17, 2016Assignee: Cypress Semiconductor CorporationInventors: Kimihiko Hosaka, Toro Anezaki
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Patent number: 9343666Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.Type: GrantFiled: June 21, 2012Date of Patent: May 17, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Suzette K. Pangrle, Steven Avanzino, Sameer Haddad, Michael Vanbuskirk, Manuj Rathor, James Xie, Kevin Song, Christie Marrian, Bryan Choo, Fei Wang, Jeffery A. Shields
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Patent number: 9334578Abstract: An electroplating system is provided. The electroplating system includes a divided electrode that is arranged to simultaneously provide a plurality of line currents for an electroplating process. The system includes a current control component that is coupled to the divided electrode. The current control component is configured to determine the magnitude of each of the line currents. The current control component is also configured to regulate individual line currents based, at least in part, on the determined magnitude of each of the line currents.Type: GrantFiled: November 18, 2008Date of Patent: May 10, 2016Assignee: Cypress Semiconductor CorporationInventor: Naoki Takeguchi
