Abstract: A semiconductor device includes an oxide-nitride-oxide (ONO) dielectric stack on a surface of a substrate, and a high work function gate electrode formed over a surface of the ONO dielectric stack. The ONO dielectric stack includes a multi-layer charge storage layer including a silicon-rich, oxygen-lean top silicon nitride layer and an oxygen-rich bottom silicon nitride layer. The high work function gate electrode includes a P+ doped polysilicon layer.

Abstract: A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein the memory device interface comprises an address output configured to transmit address values, a write data output configured to transmit write data on rising and falling edges of a periodic signal, and a read data input configured to receive read data at the same rate as the write data.

Abstract: There is provided a method of fabricating a semiconductor device including forming a first film on a base layer, forming a first mask pattern on the first film, the first mask pattern having mask portions arranged at a given pitch, forming first sidewall films on sidewalls of the first mask pattern by etchback of a deposited second film, removing the first mask pattern, and forming a second mask pattern composed of the first sidewall films and second sidewall films defined by etchback of a deposited third film. It is possible to form a stripe pattern with the line width and the line space thereof having the same sizes and at a pitch the same as the minimum process size determined by the photolithographic performance, thereby enabling fabrication of a semiconductor device with a high degree of integration.

Abstract: An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.

Abstract: A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract: Systems, methods, and apparatus for force sensor baseline calibration are disclosed herein. 1. Apparatus may include a force sensor configured to receive a plurality of force signals from a plurality of force sensitive elements, where the plurality of force signals is associated with a first touch at a first location of a sensing surface. The apparatus may include a touch sensor configured to receive a touch signal associated with the first touch. The apparatus may include processing logic coupled to the force sensor and the touch sensor, the processing logic being configured to determine a magnitude of a first component force associated with the first touch based, at least in part, on the plurality of force signals and the touch signal. The first component force may characterize a force applied by the first touch at the first location of the sensing surface.

Abstract: An apparatus and method for providing an active feedback of a position of a conductive object, manipulated by a user on a sensing device, to allow detection of a reference location on the sensing device by the user. The apparatus may include a sensing device to detect a presence of a conductive object, manipulated by a user on the sensing device, a processing device coupled to the sensing device, the processing device to determine a position of the conductive object on the sensing device, and a feedback mechanism coupled to the processing device to provide an active feedback to the user to allow detection of a reference location on the sensing device by the user.

Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.

Abstract: A training device that includes a receiving surface on its handle, multiple capacitive sensor elements disposed within multiple grip areas on the receiving surface, a sense circuit configured to compare the capacitance measurements with threshold capacitance values and generate a signal when the capacitance measurements indicate a touch on the grip area and an indicator.

Abstract: An electronic device includes a packaged integrated circuit having an integrated circuit die having an active surface, and a molding compound overlaying the active surface of the integrated circuit die. In a particular embodiment, the packaged integrated circuit includes at least approximately five weight percent (5 wt %) zinc relative to the molding compound. In another embodiment, the packaged integrated circuit includes approximately 0.3 ?mol/cm2 of zinc in an area parallel to the active surface of the integrated circuit die.

Abstract: An apparatus having a processing device for calibrating a touch-sensor device with calibration capacitors is described. Methods of calibrating the touch-sensor device using the same are also described. Processing device and multiple calibration capacitors are disposed on an integrated circuit (IC) die substrate. The processing device includes a measurement circuit to be coupled to a touch-sensor device and a switching circuit to selectively couple the calibration capacitors to the measurement circuit. The processing device is configured to calibrate the touch-sensor device by applying one or more capacitance touch values from one or more of the calibration capacitors using the switching circuit. The one or more capacitance touch values simulate a touch on the touch-sensor device.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Abstract: Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

Abstract: Structures and methods for blocking ultraviolet rays during a film depositing process for semiconductor device are disclosed. In one embodiment, a semiconductor device includes an oxide-nitride-oxide (ONO) film formed on a semiconductor substrate, a gate electrode formed on the ONO film, a lower layer insulation film formed on the ONO film and the gate electrode, and a ultraviolet (UV) blocking layer based on a plurality of granular particles scattered in at least one insulation film formed on lower layer insulation film, where the UV blocking layer suppresses UV rays generated during an additional film deposition from reaching the ONO film.

Abstract: Systems, methods, and devices are disclosed for implementing a bootstrapped power circuit. Devices may include a controller configured to generate an output signal. Devices may include a power converter configured to receive the output signal, configured to store an amount of energy in response to receiving the output signal, and further configured to release the amount of energy in response to detecting a change in the output signal. Devices may include a switch configured to be toggled between a first and second position. Devices may include a power source configured to store a second voltage having a second amplitude. Devices may include a bootstrap circuit configured to receive a third voltage from the power source when the switch is in the first position, and configured to receive at least some of the amount of energy from the power converter when the switch is in the second position.

Abstract: Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions formed in the semiconductor layer at both sides of the trench.

Abstract: A crystal oscillation circuit is provided with a crystal oscillator, an inverter unit coupled in parallel with the crystal oscillator and including a plurality of inverters, a current supply unit that supplies current to at least a first inverter of the plurality of inverters, a signal converter that supplies current to at least a last inverter of the plurality of inverters and outputs a voltage to an external circuit, and a current controller that makes the current supply unit provide current corresponding to a voltage level of the output voltage of the signal converter. The crystal oscillation circuit is capable of reducing power consumption.