Abstract: A computer system that includes a central processing unit, a random-access-memory interface, a random-access memory whose addresses are allocated in an address space of the random-access-memory interface, and a reconfigurable arithmetic device is described herein. The reconfigurable arithmetic device includes input terminals, output terminals, a network of plurality of processor elements, a built-in random-access memory, a control unit, an inter-processor-element network and a configuration-data memory. In accordance with configuration on data from the configuration-data memory, the inter processor-element network is capable of changing the connection state of the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, and the arithmetic function of the reconfigurable arithmetic device is capable of being dynamically changed.

Abstract: A voice activation system is provided. The voice activation system includes a first stage configured to output a first activation signal if at least one energy characteristic of a received audio signal satisfies at least one threshold and a second stage configured to transition from a first state to a second state in response to the first activation signal and, when in the second state, to output a second activation signal if at least a portion of a profile of the audio signal substantially matches at least one predetermined profile.

Abstract: Selecting an array from among a plurality of arrays in a memory as a reference array. An exemplary method includes evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating and the selecting to select a second reference cell from within the reference array, the second reference cell being associated with a second operation of the memory.

Abstract: A communication apparatus includes a storage part configured to store a first key generated according to authentication with a transmission source, identification information of the transmission source, and first information remaining unchanged regardless of the initialization of a coupling status and corresponding to the transmission source, with the first key, the identification information and the first information mapped to each other, an acquisition part configured to acquire a public key from the transmission source holding the identification information responsive to the first information stored on the storage part if the identification information of the transmission source has changed in response to the initialization of the coupling status, and a calculation part configured to generate an encryption key for use in encryption and decryption of data transmitted by the transmission source, based on the first key responsive to the first information, and the public key.

Abstract: A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased.

Abstract: A method and apparatus receive multiple data pattern analysis requests from a controller and substantially simultaneously perform, with multiple data pattern analysis units, multiple data pattern analyses on one or more portions of a data stream.

Abstract: A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array.

Abstract: A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.

Abstract: A method may include selecting at least an initial communication mode from a plurality of communication modes that each communicate with a master device using time division multiple access (TDMA); and dynamically switching communication modes between the master device and at least slave device in accordance with at least one predetermined characteristic of the wireless system.

Abstract: A method of operation of a real-time data-pattern analysis system includes: providing a memory module, a computational unit, and an integrated data transfer module arranged within an integrated circuit die; storing a data pattern within the memory module; transferring the data pattern from the memory module to the computational unit using the integrated data transfer module; and comparing processed data to the data pattern using the computational unit.

Abstract: A capacitance sensing system can filter noise that presents in a subset of electrodes in the proximity of a sense object (i.e., finger). A capacitance sensing system can include a sense network comprising a plurality of electrodes for generating sense values; a noise listening circuit configured to detect noise on a plurality of the electrodes; and a filtering circuit that enables a filtering for localized noise events when detected noise values are above one level, and disables the filtering for localized noise events when detected noise values are below the one level.

Abstract: A line plotting method for plotting lines whose coordinates are given on a display screen on which pixels are arranged according to a prescribed rule, the method includes correcting coordinates at the end point of a line on the basis of which the end point is a starting point or an ending point or whether the end point is inside a prescribed frame determining whether a direction from a starting point of a line after correction toward its ending point horizontally or vertically is the same as a direction from a starting point before correction of a line toward its ending point determining whether integer values of the coordinates of starting and ending points after correction are the same when directions from starting points after and before correction of a line toward their ending points are not matched.

Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Abstract: Apparatuses and methods of driving barrier electrodes of a capacitive-sense array with an excitation signal are described. One apparatus includes a capacitance-sensing circuit coupled to a capacitive-sense array including multiple electrodes. The capacitance-sensing circuit includes multiple sensing channels. The capacitance-sensing circuit is operative to measure signals on a first subset of the multiple electrodes using the multiple sensing channels. Each of the sensing channels is selectively coupled to one of the first subset of electrodes. The capacitance-sensing circuit is further operative to drive a barrier electrode of the multiple electrodes with an excitation signal while measuring the signals on the first subset. The excitation signal is greater in magnitude than the measured signals. The barrier electrode is adjacent to an edge electrode of the first subset that is coupled to one of the sensing channels.

Abstract: A device including both drain extended metal-on-semiconductor (DE_MOS) and low-voltage metal-on-semiconductor (LV_MOS) transistors and methods of manufacturing the same are provided. In one embodiment, the method includes implanting ions of a first-type at a first energy level in a drain portion of a first DE_MOS transistor in a DE_MOS region of a substrate to form the first DE_MOS transistor, and implanting ions of the first-type at a second energy level in a LV_MOS region of the substrate adjust a voltage threshold of a first LV_MOS transistor, while concurrently implanting ions of the first-type at the second energy level in the drain portion of the first DE_MOS transistor to form a drain extension of the first DE_MOS transistor. Other embodiments are also provided.

Abstract: A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.

Abstract: A method of driving an output terminal to a voltage, in which an input signal is received, an appropriate output voltage and output voltage range are determined based on the input signal, an output driver is configured to a first mode and the output driver drives the output terminal to a voltage within the voltage range, the output driver is configured to a second mode and the output driver drives the output terminal to a voltage approximately equal to the appropriate output voltage.

Abstract: USB physical interface subsystems are provided that include a protection circuit including a power supply interface and a plurality of pin interfaces, a pin identifier circuit in communication with the protection circuit for detecting a device coupling to a pin connected to one pin interface of the plurality of pin interfaces, a USB physical interface, and a dual power supply regulator configured to receive power via the power supply interface, to continuously supply a first voltage to the protection circuit, and to provide a second voltage and a third voltage to the pin identifier circuit and the USB physical interface, the second voltage and the third voltage being switched outputs.

Abstract: A capacitive sense array configured to improve edge accuracy in detecting a presence of a conductive object is described. In one embodiment, a capacitive sense array includes at least a first set of sense elements having non-homogenous pitches disposes in a first longitudinal axis of the capacitive sense array. The pitch includes width of the sense elements and spacing between the sense elements.

Abstract: Ferroelectric capacitors used in ferroelectric random access memories (F-RAM) and methods for fabricating the same to reduce sidewall leakage are described. In one embodiment, the method includes depositing over a surface of a substrate, a ferro stack including a bottom electrode layer electrically coupled to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between. A hard-mask is formed over the ferro stack, and a top electrode formed by etching through the top electrode layer and at least partially through the ferroelectric layer. A non-conductive barrier is formed on sidewalls formed by etching through the top electrode layer and at least partially through the ferroelectric layer, and then a bottom electrode is formed by etching the bottom electrode layer so that conductive residues generated by the etching are electrically isolated from the top electrode by the non-conductive barrier.