Patents Assigned to Cypress Semiconductor
  • Hard press rejection
    Patent number: 9043183
    Abstract: Techniques for hard press rejection are described herein. In an example embodiment, a touch area on a sensor array is determined, where the touch area corresponds to a detected object and is associated with multiple signal values. A slope value for the detected object is computed based on a ratio of a signal distribution value in the touch area to a metric indicating a size of the touch area with respect to the sensor array. The slope value is compared to a threshold in order to determine whether to accept or to reject the detected object, and the detected object is rejected based on the comparison.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: May 26, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Petro Ksondzyk, Jae-Bum Ahn
  • System and method for multi-layer global bitlines
    Patent number: 9041203
    Abstract: A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: May 26, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Zubin Patel, Nian Yang, Fan Wan Lai, Alok Nandini Roy
  • Method and apparatus for staggered start-up of a predefined, random or dynamic number of flash memory devices
    Patent number: 9036423
    Abstract: A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: May 19, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Bradley Edman Sundahl, Sean Michael O'Mullan, Gregory Charles Yancey, Kenneth Alan Okin
  • DC-DC converter, control circuit, and power supply control method
    Patent number: 9035632
    Abstract: A DC-DC converter includes a first amplifier that amplifies a first difference between a first reference voltage and a feedback voltage corresponding to an output voltage, a second amplifier that amplifies a second difference between the first reference voltage and an integrated value of the feedback voltage, and a controller that controls a switching circuit to change the output voltage when the first difference reaches the second different.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: May 19, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventor: Kazuyoshi Futamura
  • Simultaneously forming a dielectric layer in MOS and ONO device regions
    Patent number: 9023707
    Abstract: Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 5, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Bo Jin, Fredrick B. Jenne
  • MULTI-CHANNEL, MULTI-BANK MEMORY WITH WIDE DATA INPUT/OUTPUT
    Publication number: 20150117091
    Abstract: An integrated circuit (IC) can include M memory banks, where M is greater than 2, and each memory bank is separately accessible according to a received address value; N channels, where N is greater than 2, and each channel includes its own a data connections, address connections, and control input connections for executing a read or write access to one of the memory banks in synchronism with a clock signal; and a controller subsystem configured to control accesses between the channels and the memory banks, including up to an access on every channel on consecutive cycles of the clock signal.
    Type: Application
    Filed: March 28, 2014
    Publication date: April 30, 2015
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Dinesh Maheshwari
  • Capacitance scanning proximity detection
    Patent number: 9019226
    Abstract: A method and apparatus for scanning a first set of electrodes of a capacitive sense array using a first sensing mode to identify a presence of an object in proximity to the capacitive sense array, where scanning using the first sensing mode identifies objects not in physical contact with the capacitive sense array. The first set of electrodes is scanned using a second sensing mode to determine a location of the object in relation to the capacitive sense array, where rescanning using the second sensing mode determines locations of objects in physical contact with the capacitive sense array.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: April 28, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Oleksandr Karpin, Andriy Maharyta, Andriy Ryshtun, Victor Kremin, Volodymyr Hutnyk
  • Baseline charge compensation
    Patent number: 9019220
    Abstract: A compensation circuit may include a current source configured to control an amplitude of a current pulse, a memory configured to store a plurality of duration values each corresponding to a set of one or more sensor electrodes of a plurality of sensor electrodes, and a pulse width controller configured to control a duration of the current pulse based on a first duration value of the plurality of duration values, and to apply the current pulse to a compensation node of a capacitance sensor during a measurement cycle for a first set of one or more sensor electrodes, where the first set of one or more sensor electrodes corresponds to the first duration value.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Hans W. Klein, Paul Walsh, Keith O'Donoghue, Roman Ogirko
  • Low pin count solution using capacitance sensing matrix for keyboard architecture
    Patent number: 9019133
    Abstract: An apparatus and method for selecting a keyboard key based on a position of a presence of a conductive object on a sensing device and a pre-defined area of the keyboard key. The apparatus may include a sensing device and a processing device. The sensing device may include a plurality of sensor elements to detect a presence of a conductive object on the sensing device. Multiple keyboard keys are assigned to pre-defined areas of the sensing device. The processing device is coupled to the sensing device using capacitance sensing pins, and may be operable to determine a position of the presence of the conductive object, and to select a keyboard key based on the position of the conductive object and the pre-defined areas of the sensing device.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: April 28, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Liu Hua, XiaoPing Jiang
  • Deuterated film encapsulation of nonvolatile charge trap memory device
    Patent number: 9018693
    Abstract: Nonvolatile charge trap memory devices with deuterium passivation of charge traps and methods of forming the same are described. In one embodiment, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. A gate stack overlies the channel, the gate stack comprising a tunneling layer, a trapping layer, a blocking layer, a gate layer; and a deuterated gate cap layer. The gate cap layer has a higher deuterium concentration at an interface with the gate layer than at surface of the gate cap layer distal from the gate layer. In certain embodiments, the channel comprises polysilicon or recrystallized polysilicon. Other embodiments are also described.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: April 28, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Fredrick Jenne, William Koutny
  • Universal digital block interconnection and channel routing
    Patent number: 9018979
    Abstract: A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 28, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Warren Snyder, Bert Sullam, Haneef Mohammed
  • Mutual capacitance sensing circuits, methods and systems
    Patent number: 9013195
    Abstract: A capacitance sensing system may include a first selection circuit that couples N electrodes of a first electrode set to a capacitance sense circuit; and a second selection circuit that couples M electrodes of a second electrode set, substantially simultaneously, to a signal generator circuit as a group to induce current in the N electrodes by mutual capacitance between the M and N electrodes; wherein N is at least one, and M>N.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: April 21, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Victor Kremin, Andriy Maharyta, Patrick Prendergast
  • Method and apparatus for data transmission via capacitance sensing device
    Patent number: 9013425
    Abstract: Methods, devices, and systems for a touch sensor or a capacitive sensing device to interact with external objects. One method utilizes a capacitive profile on the external object. Another method involves the further use of a capacitive sensor array for wireless communication with the external object.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 21, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Thomas Fuller, Cole Wilson, Jon Peterson, David G. Wright
  • Multi-stage stylus detection
    Patent number: 9013429
    Abstract: A system comprises a processing device and a capacitive sense array that includes a plurality of electrodes. The system receives a first signal from a first scan of electrodes in a capacitive sense array. The system processes the first signal using a first set of sequences to detect a stylus. The system receives a second scan from a second scan of electrodes in a capacitive sense array. The system processes the second signal using a second set of sequences to detect the stylus.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: April 21, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mykhaylo Krekhovetskyy, Ruslan Omelchuk, Viktor Kremin
  • Smart scanning for a capacitive sensing array
    Patent number: 9013441
    Abstract: A method and apparatus scan a plurality of scan groups in a capacitive sense array to generate signals corresponding to a mutual capacitance between the electrodes. Each of the plurality of scan groups is formed from a subset of the plurality of electrodes. A processing device identifies a scan group where the generated signal is affected by a presence of a conductive object. The processing device individually scans the subset of the plurality of sense elements in the identified scan group to determine a location of the conductive object.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 21, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Victor Kremin, Oleksandr Pirogov, Andriy Ryshtun
  • Systems and methods for discharging load capacitance circuits
    Patent number: 9013938
    Abstract: Circuits, systems, and methods for discharging loads are provided. One circuit includes a node coupled to a voltage source, a capacitor, a source-follower device coupled between the node and the capacitor, and a current source coupled to the capacitor. The source-follower device is configured to switchably couple the capacitor to the node to discharge the voltage source and the current source is configured to discharge the capacitor. One system includes the above circuit coupled to a memory device such that the circuit is configured to discharge voltage from the memory device. A method includes discharging, via a capacitor coupled to the memory device, a high voltage from the memory device and discharging, via a current source coupled to the capacitor, the high voltage from the capacitor. The capacitor is configured to discharge the high voltage within a predetermined range of time.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: April 21, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gary Moscaluk, John Tiede
  • Programmable input/output circuit
    Patent number: 9013209
    Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: April 21, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
  • Dynamic mode switching for fast touch response
    Patent number: 9007342
    Abstract: A method of operating a touch-sensing surface may include performing a first scan of a first set of electrodes of a touch-sensing surface, determining a presence of at least one conductive object proximate to the touch-sensing surface, in response to determining the presence of the at least one conductive object, performing a second scan of a second set of electrodes of the touch-sensing surface, and repeating the performing the second scan until the at least one conductive object is no longer proximate to the touch-sensing surface.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: April 14, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Edward Grivna, Jason Baumbach, David Bordui, Weibiao Zhang, MingChan Chen, Tao Peng
  • Internal data compare for memory verification
    Patent number: 9007843
    Abstract: A method and apparatus to program data into a row of a non-volatile memory array and verify, internally to the non-volatile memory array, that the data was successfully programmed. The verification includes comparing the programmed data from the row of the non-volatile memory array to data in the plurality of high voltage page latches that were used to program the row.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 14, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ryan T. Hirose, John W. Tiede, Iustin Ignatescu
  • Touch sensor pattern
    Patent number: 9007333
    Abstract: A capacitive sensor array may include a first plurality of sensor elements and a second sensor element. The second sensor element may include a main trace intersecting each of the first plurality of sensor elements to form a plurality of intersections each associated with a unit cell, where a contiguous section of the main trace crosses at least one of the plurality of unit cells. An area within the unit cell may include at least a portion of one or more primary subtraces branching from main subtrace, a plurality of secondary subtraces branching away from the one or more primary subtraces, and at least one tertiary subtrace branching away from at least one of the secondary subtraces.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: April 14, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Cole Wilson, Patrick Prendergast, Jon Peterson