Abstract: An apparatus includes a data conditioning module configured to translate each of a plurality of signal strength values to a compensated signal value, where the compensated signal value is a function of its corresponding signal strength value.

Abstract: Disclosed herein is an apparatus that includes a ferrocapacitor having a sidewall. An etch stopping film is disposed along the sidewall of the ferrocapacitor, with a hydrogen barrier film disposed between the etch stopping film and the sidewall of the ferrocapacitor.

Abstract: Touch sensor methods, devices and systems are disclosed. One embodiment of the present invention pertains to a touch sensing system comprising a sensing device for sensing one or more touches on a sensor surface made of multiple conductive strips in one direction and a dual processing device for determining a horizontal position and a vertical position of each touch by processing currents generated in response to the touch, where the currents charge and discharge a capacitor formed between the touch and the sensor surface.

Abstract: An embodiment of the present invention is directed to a semiconductor packaging frame allowing identification information to be stored in the paddle area of the individual frame. Forming identification information on the paddle allows unique tracking of the semiconductor frame package during and after manufacturing and for tracking down variances, defects, and other problems during the semiconductor packaging process. Further, the shapes formed from the identification information provide increased surface area for bonding of the molding compound and thus strengthen the bond between the die paddle and molding compound thereby improving the strength of the semiconductor package.

Abstract: Techniques for reducing post-routing delay variance are described herein. In an example embodiment, an initial netlist includes multiple instances that represent digital components of an electronic design. An base signature is assigned to each instance in the initial netlist, where the base signature is based on two or more design or connectivity attributes of the instance. The base signatures are then used to generate an initial instance ordering of the instances in the initial netlist. A subsequent netlist, different from the initial netlist but representing the same electronic design, is received. Base signatures are assigned to the instances on the subsequent netlist and a subsequent instance ordering is generated. The subsequent instance ordering preserves the same order as the initial instance ordering for those instances that are included in both the initial netlist and the subsequent netlist. In this manner, any later netlist-based processing (e.g.

Abstract: A method and apparatus receive a plurality of signal values, the plurality of signal values responsive to an input object. The method and apparatus calculate at least one signal ratio value using the plurality of signal values and determine a position of the input object using the at least one signal ratio value.

Abstract: A clock synthesis system may include a feed forward divider circuit configured to divide a source clock signal by one of a plurality of integers in response to a select signal to generate a reference clock that is synchronous to a synchronous pulse; a modulator that modulates the select signal in response to at least a difference value; a multiplier circuit that frequency multiplies the reference clock to generate an output clock; and a timing circuit that generates the difference value in response to the source clock and synchronous pulse.

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

Abstract: A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising logic circuits responsive to the processor, the scheduler circuit configured to transfer data packets to the at least one data channel via a packet based serial data communication interface and according to the first data structure.

Abstract: Methods, physical computer-readable media, and devices are provided that allow re-enumeration to be initiated on a USB 3.0-compatible device. The method includes establishing a connection with a host, transmitting an indicator from the device to the host to cause a Link Training and Status State Machine (LTSSM) of the host to move from active state (U0) to one of SS.Inactive and RX.Detect, synchronizing the device with the host, and presenting a new configuration of the device to the host.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.

Abstract: An apparatus includes an array of universal digital blocks (UDBs) and a central processing unit (CPU) coupled to the array of UDBs via a bus. The UDBs may be coupled together to perform tasks, operations or functions that may be offloaded from the CPU to the array of UDBs.

Abstract: Embodiments described herein provide capacitive sensor arrays. The capacitive sensor arrays include a plurality of column sensor elements arranged in a plurality of columns and a plurality of row sensor elements arranged in a plurality of rows. The plurality of rows and the plurality of columns are arranged such that each of the row sensor elements is at least partially within a gap between adjacent ones of the column sensor elements. A capacitance between a first portion of one of the columns and an adjacent first portion of one of the rows is greater than a capacitance between a second portion of one of the columns and an adjacent second portion of one of the rows.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: An adaptive algorithm running on a processing device receives a temperature value that represents a temperature at a gate terminal of a transistor. The adaptive algorithm, determines a drive strength value that represents a drive strength for a signal based on the temperature value. A signal with the determined drive strength is applied to the gate terminal of the transistor.

Abstract: A method and apparatus receive first input through a touch screen and communicate over a cellular network responsive to the first input. The method and apparatus receive second input through the touch screen and use the second input to control, through a wireless network other than the cellular network, an image displayed on a screen of a second device.

Abstract: A processing system measures an input voltage received at an input of an analog circuit, such as an analog-to-digital converter (ADC), where the input voltage is measured by comparing the input voltage to a reference voltage. The reference voltage is determined by the difference between a first voltage and a ground voltage. The processing system includes a programmable reference signal selection circuit to maintain the reference voltage at a constant level.

Abstract: A method for device driver self authentication is provided. The method includes accessing a device driver having encrypted authentication parameters therein including, for instance, a vendor identification, a device identification, a serial number, an expiration date and a filename. The method includes executing an authentication portion of the device driver to generate a message digest of these parameters and comparing the message digest to a stored digest for a match thereof. The method further includes loading the device driver only if the authentication portion successfully authenticates the device driver, e.g., there is a match. The method can be applied to USB device drivers and peripherals.

Abstract: A method, apparatus, and system to detect a self-capacitance activation in view of a self-capacitance measurement of a first electrode. The method, apparatus, and system further to detect a mutual capacitance activation in view of a mutual capacitance measurement of a pair of electrodes, and to determine the presence of water proximate to the capacitive button when the self-capacitance activation is false and the mutual capacitance activation is true. The capacitive button is disposed on a substrate.