Abstract: A processing device scans, during a first operation, a first plurality of electrodes along a first axis in a capacitive sense array to generate a first plurality of signals corresponding to a mutual capacitance at electrode intersections of the capacitive sense array. During a second operation, the processing device scans a second plurality of electrodes along a second axis in the capacitive sense array to generate a second plurality of signals corresponding to the mutual capacitance at the electrode intersections of the capacitive sense array, wherein the second operation occurs during a different period of time than the first operation. The processing device determines a first coordinate of a conductive object proximate to the capacitive sense array based on the first plurality of signals and a second coordinate of the conductive object based on the second plurality of signals.

Abstract: A shallow bipolar junction transistor comprising a high voltage n+ well implanted into a semiconductor substrate. The shallow bipolar junction transistor further comprises a bit line n+ implant (BNI) above the high voltage n+ well and an oxide nitride (ONO) layer above the high voltage n+ well. A portion of the ONO layer isolates the BNI from a shallow trench isolation (STI) region.

Abstract: A capacitance measurement sensor, having a voltage subtractor that rejects common signals between the columns or rows of a touch sensor matrix depending on which are driven and which are being sensed, is described.

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Abstract: Apparatuses and methods of synchronizing a display driver integrated circuit (DDI) and a touch screen controller (TSC) integrated circuit that are coupled to a display integrated touch panel, such as an in-cell panel, and allowing multi-phase transmit (TX) scanning of the in-cell touch panel. One apparatus includes a DDI configured to receive signals on a video interface from a host processor over a video interface and to drive electrodes of a touch panel. The DDI is configured to receive control signals from a TSC over a control interface to drive different transmit (TX) phase sequences of a TX signal in different sensing interval on the electrodes of the touch panel.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

Abstract: Optical navigation modules and methods of operating the same to sense relative movement between the optical navigation module and a tracking surface are provided. In one embodiment, the optical navigation module comprises: (i) a light source to illuminate at least a portion of a surface relative to which the optical navigation module is moved; (ii) an integrated circuit (IC) including a photo-detector array (PDA) to detect a light pattern propagated onto the PDA from the surface, and a signal processor to translate changes in the light pattern propagated onto the PDA into data representing motion of the optical navigation module relative to the surface; and (iii) a substrate to which the light source and IC are mounted, the substrate including an aperture in a light path between the surface and the PDA. Other embodiments are also disclosed.

Abstract: A method and apparatus to increase a transmit (TX) signal generated by an active stylus without increasing the power consumption of the active stylus. In one aspect, the active stylus increases the amplitude of the TX signal. In another aspect, the active stylus increases the TX signal by providing the capacitance of a body of a user to the stylus.

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer. The second nitride layer is oxygen-rich relative to the second nitride layer and includes a majority of the charge traps. Other embodiments are also described.

Abstract: Embodiments of optical navigation modules (ONM) and methods of operating the same to block auto-movement due to ambient light are described. Generally, the method includes: (i) collecting a plurality of PD signal samples from a photodiode (PD) in an optical navigation module (ONM); (ii) determining a peak-to-peak variation (?PD) in the plurality of PD signal samples; (iii) comparing the peak-to-peak variation (?PD) to a specified threshold peak-to-peak variation (?PDSPEC); and (iv) if ?PD is less than ?PDSPEC, suppressing reporting of motion data derived from signals from a photodetector array (PDA) in the ONM to block auto-movement in an output from the ONM. Other embodiments are also described.

Abstract: A device is configured to establish first and second device power domains. Isolation circuits isolate signals from passing between circuits in the first device power domain and circuits in the second device power domain. During a transition between power domains, an n-bit value is stored in a particular storage location, and compared to a particular n-bit value. Isolation between the first and second device power domains is removed when the n-bit value stored in the particular storage location matches the particular n-bit value.

Abstract: A configurable bus includes a plurality of bus segments. The configurable bus also includes two or more pluralities of input/output (I/O) ports. Each bus segment is coupled to at least one of the pluralities of I/O ports. Also coupled to the bus segments is a cross-couple unit that is configurable to selectively couple any of the bus segments together.

Abstract: A method for improving noise immunity of capacitive sensing circuit associated with a touch sense array is disclosed. The capacitive sensing circuit receives a response signal from a touch sense array. The capacitive sensing circuit measures a noise component of the response signal. When a level of noise of the noise component within a passband of the capacitive sensing circuit is greater than a threshold, the capacitive sensing circuit changes at least one parameter of capacitive sensing circuit to move the passband substantially outside the frequency spectrum of the noise component.

Abstract: A serial interface includes a select node, a clock node, a first bidirectional data port, a second bidirectional data port, and shift register circuitry coupled to both data ports such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift or transfer data.

Abstract: A memory device is described. Generally, the device includes a memory transistor and a metal oxide semiconductor (MOS) logic transistor. The memory transistor includes: a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon; an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer; and a gate electrode comprising doped polysilicon formed over a surface of the ONNO stack. The MOS logic transistor includes a gate oxide and a gate electrode comprising doped polysilicon. Other embodiments are also described.

Abstract: A method of operating a touch-sensing surface may include determining a presence of at least one conductive object at the touch-sensing surface by performing a search measurement of a first set of sensor elements of the touch-sensing surface, and in response to determining the presence of the at least one conductive object, determining a location of the at least one conductive object by performing a tracking measurement of a second set of sensor elements of the touch-sensing surface.

Abstract: Stylus tip configurations may reduce shadow effect of the stylus tip on capacitance measurements by reducing capacitive coupling between undesired portions of the stylus tip and the capacitive sensing surface. Additionally signal-to-noise ratio (SNR) of a stylus on a plurality of capacitance sensing electrodes may be improved by reducing the self capacitance between the stylus tip and the receive electrodes of a mutual capacitance touch screen.

Abstract: Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.

Abstract: An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.

Abstract: Techniques for hard press rejection are described herein. In an example embodiment, a touch area on a sensor array is determined, where the touch area corresponds to a detected object and is associated with multiple signal values. A slope value for the detected object is computed based on a ratio of a signal distribution value in the touch area to a metric indicating a size of the touch area with respect to the sensor array. The slope value is compared to a threshold in order to determine whether to accept or to reject the detected object, and the detected object is rejected based on the comparison.