Abstract: An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.

Abstract: Buffer circuit embodiments are described. A buffer circuit includes an input configured to receive an input signal and a buffer configured to generate an output signal based on the input signal. In one embodiment, the buffer circuit includes a programmable chopping module coupled with the buffer, wherein the programmable chopping module is programmable with a selected configuration from a plurality of configurations, and wherein the programmable chopping modulates the input signal based on the selected configuration. In another embodiment, the buffer circuit further includes a programmable output filter coupled with the buffer, wherein the programmable output filter is programmable with a selected configuration form a plurality of configurations, and wherein the programmable output filter filters a frequency band of the output signal based on the selected configuration.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.

Abstract: Systems, methods, and devices are disclosed for implementing frequency calibration circuits. The devices may include a data source configured to generate a first data signal based on a first data value and a second data signal based on a second data value. The devices may include a gain control circuit configured to receive the first and second data signals from the data source, and generate a first modified data signal and a second modified data signal. The devices may include an oscillator circuit configured to generate a first output signal and a second output signal based, at least in part, on the first and second modified data signals. The devices may include a calibration circuit configured to determine an adjustment value based on the first and second output signals, and further configured to change a gain of the gain control circuit based on the determined adjustment value.

Abstract: A method and system for detecting a presence of a conductive object proximate to a capacitive sense element during an initialization process of a touch-sensing device. A reference sense element is calibrated to produce a sensing parameter value. A capacitance of a plurality of capacitive sense elements is measured based on the sensing parameter value, and compared to a baseline capacitance value stored in a non-volatile memory of the touch-sensing device. The presence of a conductive object proximate to a capacitive sense element is detected when a difference between the measured capacitance and the stored baseline capacitance value is greater than a threshold value.

Abstract: A stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space. By storing some of the associated stacks in complementary metal oxide semiconductor (CMOS) or other volatile memory, read/write operations to only F-RAM would be obviated. As compared to an all F-RAM stack implementation, a faster, less power consuming and faster program execution time is provided. Firmware code can also be provided that will tend to concentrate the more intensive calculations to that part of the stack that is in volatile memory and minimize POP/PUSH operations to the F-RAM portion of the stack. Moreover, since only the top of the stack is maintained in volatile memory, most of it remains in F-RAM which means the application can still benefit from the high F-RAM endurance and shorter power-down times.

Abstract: A method of generating an application programming interface (API) for an electronic circuit. A graphical user interface is displayed through which a user can initiate generation of the API. A component is selected from a plurality of components for placement in said electronic circuit. The component represents an implementable function in the electronic circuit. The component is configured using the graphical user interface. The data pertaining to the selected component and the configuration of the component is stored. The graphical user interface is utilized to access the stored data. The interface is initiated to invoke a processing of said data which causes a generation of the application programming interface. The application interface is for controlling the function of the component in said electronic circuit.

Abstract: Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.

Abstract: Methods and apparatuses of a multi-purpose stylus antenna are described. One device includes a processing device comprising a switch, an antenna circuit, and a capacitance sensor. The switch is configured to couple a conductive element between the antenna circuit and the capacitance sensor. The processing device is configured to communicate data to or from a stylus when the switch is coupled to the antenna circuit and to measure capacitance associated with the conductive element when the switch is coupled to the capacitance sensor.

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer. The second nitride layer is oxygen-rich relative to the second nitride layer and includes a majority of the charge traps. Other embodiments are also described.

Abstract: A method of encapsulating a ferroelectric capacitor or ferroelectric memory cell includes forming encapsulation materials adjacent to a ferroelectric capacitor. forming a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and forming an FEO encapsulation layer over the ferroelectric oxide to provide additional protection from hydrogen induced degradation.

Abstract: Methods of forming memory cells including non-volatile memory (NVM) and MOS transistors are described. In one embodiment the method includes: depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate of a NVM transistor, the dielectric stack including a tunneling layer overlying a surface of the substrate, a charge-trapping layer overlying the tunneling layer and a blocking layer overlying the charge-trapping layer; forming a mask exposing source and drain (S/D) regions of the NVM transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the blocking layer and at least a first portion of the charge-trapping layer in S/D regions of the NVM transistor; and implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack to form a lightly-doped drain adjacent to the gate of the NVM transistor.

Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Abstract: Over-voltage tolerant circuits and methods are provided. In one embodiment, the circuit includes a pull-up transistor coupled to an I/O pad, a sensing circuit coupled to the I/O pad and to a voltage supply (Vcc), the sensing circuit configured to sense a voltage applied to the pad (Vpad), a latch coupled to the sensing circuit to retain an output of the sensing circuit, and a selection circuit coupled to the sensing circuit through the latch. The selection circuit includes a first bias circuit to apply Vcc to a well and gate of the pull-up transistor, a second bias circuit to apply Vpad to the gate and the well of the pull-up transistor, and a non-overlap circuit configured to ensure the gate and the well of the pull-up transistor is substantially always driven by either the first or the second bias circuit depending on the output of the sensing circuit.

Abstract: Power management architectures, methods and systems for programmable integrated circuit are disclosed. One embodiment of the present invention pertains to a power management software architecture which comprises power management modules each associated with a respective driver. Each driver is associated with a component of a programmable integrated circuit and displayable as a graphic image within an on-screen display of an integrated circuit design tool for programming the programmable integrated circuit. In addition, each power management module is operable to report power consumption data customized to its respective driver. The power management software architecture also comprises a power source module associated with a power source for the programmable integrated circuit for reporting power supply characteristics.

Abstract: Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.

Abstract: A circuit includes a switched modulator stage combining an information signal with a square wave carrier to produce a first modulated signal; and a second modulation stage forming additional steps in the first modulated signal to produce a second modulated signal.

Abstract: An apparatus for and method of resolving multiple presences over a touch sensor are described. The method includes logically grouping data from a touch sensor array in order to convert the data into X-Y coordinates.

Abstract: An apparatus and method for preventing unintentional activation of the one or more touch-sensor buttons caused by a presence of conductive liquid on the touch panel. The apparatus may include a processing device to prevent unintentional activations of one or more touch-sensor buttons caused by a presence of conductive liquid on the one or more touch-sensor buttons.

Abstract: One embodiment of a capacitive sensor array may comprise a first plurality of sensor elements and a second sensor element comprising a main trace, where the main trace intersects each of the first plurality of sensor elements to form a plurality of intersections. A unit cell may be associated with each of the intersections, and each unit cell may designate a set of locations nearest to the corresponding intersection. A contiguous section of the main trace may cross at least one of the plurality of unit cells. Within each unit cell, the second sensor element may comprise at least one primary subtrace branching away from the main trace.