Abstract: Apparatuses and methods of sense arrays with non-uniform patterns are described. One capacitive-sense array includes a first set of electrodes and a second set of electrodes. The first set of electrodes intersect the second set of electrodes to form a unit cells each corresponding to an intersection of a pair of electrodes comprising one electrode from the first set and one electrode from the second set. At one of the second set of electrodes includes a non-uniform conductive pattern including a first region being located at the intersection of the respective unit cell and a distal region being at a location within the respective unit cell that is farther away from the intersection than the first region. The first region includes a first conductive surface area and the distal region includes a second conductive surface area that is greater than the first conductive surface area.

Abstract: Techniques for eliminating tail effect are described herein. In an example embodiment, a device comprises a sensor coupled with a processing logic. The sensor is configured to measure a plurality of measurements from a sensor array when the sensor array is in an unsettled state, where the measurements represent a conductive object that is proximate to a touch-sensing surface of the sensor array. The processing logic is configured to determine a set of adjustment values that correspond to a tail effect associated with the plurality of measurements, and to generate adjusted measurements corresponding to the plurality of measurements based on the set of adjustment values.

Abstract: Techniques for correcting tail effect are described herein. In an example embodiment, a device comprises a sensor coupled with a processing logic. The sensor is configured to measure a plurality of measurements from a sensor array, where the measurements are representative of a conductive object that is in contact with or proximate to the sensor array. The sensor array comprises RX electrodes and TX electrodes that are interleaved without intersecting each other in a single layer on a substrate of the sensor array. The processing logic is configured to determine a set of adjustment values that correspond to a tail effect associated with the measurements, and to generate adjusted measurements based on the set of adjustment values, where the adjusted measurements correct a parasitic signal change of the tail effect.

Abstract: Finger navigation methods, devices and systems are disclosed. In one embodiment the system comprises a light source configured to radiate a light beam towards a tactile surface. The system also comprises a photo detector module configured to sense speckle beams emitted by a target surface navigating the tactile surface in response to light hitting the target surface. The system further comprises a processor configured to track a movement of the target surface with respect to the tactile surface based on output from the photo detector module and a conductor structure for capacitive sensing of the target surface with respect to the tactile surface. The conductor structure is configured to determine a plurality of navigational functionalities based on the capacitive sensing of the target surface with respect to the tactile surface, including at least one of single click, double click, and scrolling.

Abstract: Apparatuses and methods of input attenuator circuits are described. One sensing circuit includes an attenuator circuit to receive a signal from an electrode of a sense array. The attenuator circuit is configured to attenuate input current of the signal. The attenuator circuit includes an attenuation matrix including an input terminal to receive the signal and multiple resistors. The attenuation matrix is configured to split the input current into an output current of the attenuation signal on a first output terminal and a second output current on a second output terminal. The attenuation matrix is to output the attenuated signal on the first output terminal to an integrator of the sensing circuit. The attenuator circuit also includes a buffer coupled between the attenuation matrix and the integrator. The buffer is configured to maintain a substantially same voltage at the first output terminal and the second output terminal.

Abstract: A capacitance sensing system can include a noise detector coupled to a capacitance sensing network that generates a noise detect signal in response to noise; a delay circuit coupled to generate at least two different delayed sense signals in response to outputs from the capacitance sensing network; and a switch circuit that selectively outputs one of the delayed sense signals in response to the noise detect signal. Particular embodiments can include selectively discarding discrete analog samples of a capacitance signal when noise is detected in such a sample.

Abstract: An apparatus for and a method of sensing capacitance of one or more sensor elements in multiple capacitance sensing modes, including a self-capacitance sensing mode and a mutual capacitance sensing mode.

Abstract: Apparatuses and methods for coupling a group of sensor elements together in one mode to collectively measure a capacitance on the group of sensor elements, in addition to individually measuring a capacitance on each of the sensor elements in another mode. The touch-sensor buttons may be used individually for button-activation sensing, and the touch-sensor buttons may be used collectively for proximity detection. The touch-sensor buttons and a ground conductor that surrounds the touch-sensor buttons may also be collectively used for proximity detection. The apparatus may include a processing device, and a plurality of sensor elements that are individually coupled in a first mode for button-activation sensing and collectively coupled in a second mode for proximity sensing.

Abstract: A circuit includes first logic that generates a first signal suitable to activate at least one ESD clamp in response to an electrostatic discharge (ESD) event having a first severity or a second severity higher than the first severity, and second logic that generates a second signal suitable to activate the ESD clamp in response to the ESD event having the second severity, the second signal time multiplexed with the first signal.

Abstract: Touch sensor methods, devices and systems are disclosed. One embodiment of the present invention pertains to a touch sensing system comprising a touch screen having an array of multiple conductive nodes. A shape of each conductive node is designed such that a touch to a target conductive node generates a low capacitance on one or more neighboring conductive nodes of the target conductive node and a high capacitance generated on the target conductive node. The touch sensing system further may comprise a processor coupled to the touch screen for locating the touch by processing the low capacitance and the high capacitance, where the conductive nodes are coupled to their respective input/output (I/O) pins associated with the processor. Additionally, within the array, each target conductive node coupled to the same I/O pin may comprise a different neighboring conductive node.

Abstract: Apparatuses and methods of hardware de-convolution for multi-phase scanning of a touch arrays are described. One apparatus includes a memory device configured to store a capacitance map including convolved capacitance data. The convolved data are results of multi-phase transmit (TX) scanning of a sense array with multiple TX patterns. The apparatus further comprises a de-convolution circuit block coupled to the memory device. The de-convolution circuit block is configured to de-convolve the convolved capacitance data with inverses of the multiple TX patterns to obtain capacitance data for a de-convolved capacitance map.

Abstract: Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method comprises: (i) forming an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate in at least a first region in which a non-volatile memory transistor is to be formed, the ONO dielectric stack including a multi-layer charge storage layer; (ii) forming an oxide layer on the surface of the substrate in a second region in which a metal oxide semiconductor (MOS) logic transistor is to be formed; and (iii) forming a high work function gate electrode on a surface of the ONO dielectric stack. Other embodiments are also disclosed.

Abstract: A device can include a plurality of memory cells, each memory cell including at least one latch circuit coupled between two data nodes, a first nonvolatile section coupled to a first data node, and a second nonvolatile section coupled to a second data node; and each nonvolatile section including at least one switch element in series with a programmable nonvolatile element, the switch element configured to couple the nonvolatile element to the corresponding data node during a high reliability read operation of the memory cell.

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.

Abstract: A system can include an input for receiving objects having a flat shape; a capacitance sensing network comprising a plurality of capacitance sensors positioned to be proximate to the received objects; an operations section coupled to the capacitance sensing network and configured to perform predetermined operations on the objects; and a processor section coupled to receive capacitance sense values from the capacitance sensors and configured to determine the presence and features of received objects, prior to the objects being forwarded to the operations section.

Abstract: Apparatuses and methods of signal-flow aware supply routing are described. A programmable routing system is configured to route supply signals from a supply generator circuit to one or more functional blocks based on signal channels of the functional blocks.

Abstract: A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device on rising and falling transitions of at least one access clock signal; and at least one address bus configured to receive at least a portion of address values to random access locations on rising and falling transitions a timing clock signal having the same frequency as the access clock signal.

Abstract: A circuit for generating a voltage is disclosed. The voltage has an amplitude greater than an available power supply. The circuit includes a driver to supply the voltage on an output terminal to an electrode of a touch sense array. The circuit also includes a charge pump array coupled to the driver. The charge pump array includes an array of charge pumps to supply an input voltage to the driver. The circuit also includes a feedback circuit coupled to the charge pump array. The feedback circuit is configured to measure the input voltage and to select different combinations of the array of charge pumps to maintain the voltage on the output terminal.