Patents Assigned to Freescale
  • Publication number: 20140298005
    Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.
    Type: Application
    Filed: November 23, 2011
    Publication date: October 2, 2014
    Applicants: ST MICROELECTRONICS S.R.L., FREESCALE SEMICONDUCTOR, INC.
    Inventors: Carl Culshaw, Thomas Luedeke, Nicolas Grossier
  • Publication number: 20140298111
    Abstract: A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system is described. The controller comprises a hardware processor arranged to: receive a plurality of SATA data frames; identify a first primitive sequence in at least one of the plurality of SATA data frames that adversely affects a performance of the SATA system; and replace the identified first primitive sequence with a second primitive sequence in response thereto.
    Type: Application
    Filed: November 25, 2011
    Publication date: October 2, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Eran Glickman, Ron Bar, Idan Ben Ami, BENNY Michalovich
  • Publication number: 20140292252
    Abstract: A method for determining a phase angle between voltage applied to a winding of the electric motor and an electric current flowing through the winding may include receiving a signal from the electric motor, including a value of a voltage applied to a winding of the electric motor. The method may also include determining a value of an electric current flowing through the winding and determining a phase angle between the voltage applied to the winding and the electric current flowing through the winding. The method may also include determining a speed or a stall state of the electric motor.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 2, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: DANIEL LOPEZ-DIAZ, HANS GOMMERINGER
  • Publication number: 20140295639
    Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: FENG ZHOU, Frank K. Baker, JR., Ko-Min Chang, Cheong Min Hong
  • Patent number: 8847393
    Abstract: Another semiconductor device includes a first layer including a plurality of electrically conductive wires, a second layer, a plurality of non-functional via pads are included in the second layer or between the first layer and the second layer. A dangling via is included within a specified area of the first layer. The dangling vias connect one or more of the wires in the first layer to a respective one of the via pads.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Tuan S. Hoang, Puneet Sharma
  • Patent number: 8847312
    Abstract: A lateral-diffused-metal-oxide-semiconductor device having improved safe-operating-area is provided. The LDMOS device includes spaced-apart source and drain, separated by a first insulated gate structure, and spaced-apart source and body contact The spaced-apart source and BC are part of the emitter-base circuit of a parasitic bipolar transistor that can turn on prematurely, thereby degrading the SOA of prior art four-terminal LDMOS devices. Rather than separating the source and BC with a shallow-trench-isolation region as in the prior art, the semiconductor surface in the gap between the spaced-apart source and BC has there-over a second insulated gate structure, with its gate conductor electrically tied to the BC. When biased, the second insulated gate structure couples the source and BC lowering the parasitic resistance in the emitter-base circuit, thereby delaying turn-on of the parasitic transistor and improving the SOA of such 4-T LDMOS devices.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongning Yang, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 8847630
    Abstract: A driver circuit is provided that receives an ON or OFF logic control signal and further has: an output arranged to be connected to a load; a power switch, having a control terminal with a first current terminal connected to a first power supply and a second current terminal arranged to be connected to the output to drive the load; a control circuit of a first type arranged between the control terminal of the power switch and a second power supply; and a control circuit of a second type, arranged to couple the control terminal of the power switch to the first power supply when the control signal is in the OFF state.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mohammed Mansri, Kamel Abouda, Ahmed Hamada
  • Patent number: 8847804
    Abstract: A continuous time sigma delta analog to digital converter is provided. The continuous time sigma delta analog to digital converter may include, but is not limited to, an analog to digital converter having a feedback loop, and a feedback loop controller coupled to the analog to digital converter, the feedback loop controller configured to adjust delay in the feedback loop by controlling a variable delay component in the feedback loop.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brandt Braswell, Luis J. Briones
  • Patent number: 8848537
    Abstract: A token bucket management apparatus comprises a processing resource having an input for receiving profile data associated with a classified data stream. The processing resource also comprises an arithmetic unit arranged to maintain a bucket status value for a token bucket associated with the classified data stream. The arithmetic unit is a fixed point arithmetic unit that is arranged to maintain the bucket status value in accordance with a fixed point representation of non-integer numbers having a first accuracy. The arithmetic unit calculates a fixed point non-integer increment value in accordance with a fixed point representation of non-integer numbers having a second accuracy. The arithmetic unit is arranged to manipulate the calculated non-integer increment value so as to bring the second accuracy into agreement with the first accuracy, and to increment the bucket status value by the manipulated non-integer increment value.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gil Moran, Mark Glazman, Adi Katz
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8846486
    Abstract: A method of forming a semiconductor device includes defining a first type region and a second type region in a substrate, t separated by one or more inter-well STI structures; etching and filling, in at least one of the first type region and the second type region, one or more intra-well STI structures for isolating semiconductor devices formed within a same polarity well, wherein the one or more inter-well STI structures are formed at a substantially same depth with respect to the one or more intra-well STI structures; implanting, a main well region, wherein a bottom of the main well region is disposed above a bottom of the one or more inter-well and intra-well STI features; and implanting, one or more deep well regions that couple main well regions, wherein the one or more deep well regions are spaced away from the one or more inter-well STI structures.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 30, 2014
    Assignees: International Business Machines Corporation, Kabushiki Kaisha Toshiba, Freescale Semiconductors Inc.
    Inventors: Charles W. Koburger, III, Peter Zeitzoff, Mariko Takayanagi
  • Patent number: 8848480
    Abstract: A method of operating a multiport memory, which has first and second sets of word lines and bit lines for accessing a memory array, uses a first port and a second port for accesses during a first phase of a master clock and a third port and a fourth port during a second phase of the master clock. Each port has its own port clock, which clocks their own row and column addresses, that is no faster than the master clock. Assuming there is demand for it, four accesses occur for each cycle of the master clock. This has the effect of being able to be sure that a given access is complete within two cycles of the port clocks and can be operated at the rate of one access per cycle of the port clock.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Perry H. Pelley
  • Patent number: 8850232
    Abstract: A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Asaf Ashkenazi, Dan Kuzmin, Anton Rozen
  • Patent number: 8847676
    Abstract: A system that includes a polyphase filter comprises first and second gm-C filters with first and second variable biasing and a bias controller coupled to the first and second gm-C filters and configured to offset the first variable biasing and corresponding first gm of the first gm-C filter relative to the second variable biasing and corresponding second gm of the second gm-C filter to thus improve image rejection in the system. A corresponding method includes processing a signal in a complex polyphase filter and controlling biasing of the first gm-C filter stage relative to the second gm-C filter stage to provide a mismatched gm and thereby improve rejection of the image signal.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Sateh Jalaleddine
  • Patent number: 8847358
    Abstract: A bipolar transistor having an upper surface, comprises a multilevel collector structure formed in a base region of opposite conductivity type and having a first part of a first vertical extent coupled to a collector contact, an adjacent second part having a second vertical extent a third part of a third vertical extent and desirably of a depth different from a depth of the second part, coupled to the second part by a fourth part desirably having a fourth vertical extent less than the third vertical extent. A first base region portion overlies the second part, a second base region portion separates the third part from an overlying base contact region, and other base region portions laterally surround and underlie the multilevel collector structure. An emitter proximate the upper surface is laterally spaced from the multilevel collector structure. This combination provides improved gain, Early Voltage and breakdown voltages.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J Blomberg, Jiang-Kai Zuo
  • Patent number: 8847639
    Abstract: A waveform generator for providing an analog output signal to a target device includes a look-up-table (LUT) that stores a plurality of binary address values and a digital-to-analog converter (DAC) that generates the analog output signal. The waveform generator receives an input trigger signal from the target device when the target device is ready to receive the analog output signal. The waveform generator generates a synchronized input trigger signal and aligns the analog output signal with the synchronized input trigger signal by reloading the LUT with a binary address value of zero.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Alok Srivastava, Shrestha Priya
  • Patent number: 8850446
    Abstract: A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility of each task data structure out of a group of data structures to be moved from a sorted tasks queue to a ready for execution task; updating a value, during each scheduling iteration, of a queue starvation watermark value of each task data structure that is not eligible to move to a running tasks queue, until a queue starvation watermark value of a certain task data structure out of the group reaches a queue starvation watermark threshold; and generating a task starvation indication if during an additional number of scheduling iterations, the certain task data structure is still prevented from being moved to a running tasks queue, and the additional number is responsive to a task starvation watermark.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hillel Avni, Dov Levenglick, Avishay Moskowiz
  • Publication number: 20140284716
    Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.
    Type: Application
    Filed: June 11, 2014
    Publication date: September 25, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Xiaowei Ren, David C. Burdeaux, Robert P. Davidson, Michele L. Miera
  • Publication number: 20140289357
    Abstract: A data processing system comprising at least a memory unit, a first client connected to the memory unit, and a second client connected to the memory unit is proposed. The first client may comprise a first memory access unit and an information unit. The first memory access unit may read data from or write data to the memory unit at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit and a data rate limiting unit. The second memory access unit may read data from or write data to the memory unit at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit may, for example, read data packets sequentially from the memory unit, and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.
    Type: Application
    Filed: November 24, 2011
    Publication date: September 25, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Michael Staudenmaier, Yossi Amon, Vincent Aubineau
  • Publication number: 20140285175
    Abstract: A reference voltage generating circuit comprising a first bandgap voltage source arranged to output a first bandgap voltage exhibiting a first type deviation in response to a strain applied at die level in a given direction; a second bandgap voltage source arranged to output a second bandgap voltage exhibiting a second type deviation in response to a strain applied at die level in the given direction, said second type deviation being opposite to the first type deviation of the first bandgap voltage; and an adding circuit arranged to add the first bandgap voltage and the second bandgap voltage, and to output a temperature drift and strain drift compensated reference voltage.
    Type: Application
    Filed: November 4, 2011
    Publication date: September 25, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Jean Lasseuguette