Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.

Abstract: A microelectromechanical systems (MEMS) device (58) includes a structural layer (78) having a top surface (86). The top surface (86) includes surface regions (92, 94) that are generally parallel to one another but are offset relative to one another such that a stress concentration location (90) is formed between them. Laterally propagating shallow surface cracks (44) have a tendency to form in the structural layer (78), especially near the joints (102) between the surface regions (92, 94). A method (50) entails fabricating (52) the MEMS device (58) and forming (54) trenches (56) in the top surface (86) of the structural layer (78) of the MEMS device (58). The trenches (56) act as a crack inhibition feature to largely prevent the formation of deep cracks in structural layer (78) which might otherwise result in MEMS device failure.

Abstract: Method to extract timing diagrams from synchronized single- or two-photon pulsed LADA by spatially positioning the incident laser beam on circuit feature of interest, temporally scanning the arrival time of the laser pulse with respect to the tester clock or the loop length trigger signal, then recording the magnitude and sign of the resulting fail rate signature per laser pulse arrival time. A Single-Photon Laser-Assisted Device Alteration apparatus applies picosecond laser pulses of wavelength having photon energy equal to or greater than the silicon band-gap. A Two-Photon Laser-Assisted Device Alteration apparatus applies femtosecond laser pulses of wavelength having photon energy equal to or greater than half the silicon band-gap at the area of interest. The laser pulses are synchronized with test vectors so that pass/fail ratios can be altered using either the single-photon or the two-photon absorption effect. A sequence of synthetic images with error data illustrates timing sensitive locations.

Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.

Abstract: A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.

Abstract: A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of forming a semiconductor device package includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the strip.

Abstract: A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage.

Abstract: An integrated circuit (IC) includes a flip-flop that stores data when the IC is in built-in self-test (BIST) mode. The flip-flop includes a master latch connected to a slave latch, which in turn is connected to a data retention latch. A control circuit is connected to the flip-flop. During normal operation, the master latch receives a data input signal, which is transmitted through the slave latch to another flip-flop of the IC. When the control circuit initiates BIST (scan testing), data stored in the slave latch is transferred to the data retention latch. Upon completion of BIST, the data stored in the retention latch is used to restore the flip-flop to its original state.

Abstract: An electronic circuit comprises a reset input for receiving an input reset signal, a clock input for receiving a clock signal, and a reset output for providing an output reset signal. And it comprises a synchronous reset signal path comprising a synchronization unit, arranged to receive the input reset signal and provide the input reset signal synchronized with the clock signal to the reset output when the clock signal is available, and an asynchronous reset signal path arranged to provide the input reset signal to the reset output when a current clock availability information in a clock monitoring signal indicates that the clock signal is not available.

Abstract: An IC provides tracking between multiple regulated voltages. The IC includes, a voltage reference circuit, a voltage multiplier circuit, and first and second voltage regulator circuits. The voltage reference circuit generates a first reference voltage. The first voltage regulator circuit generates, at a first terminal of a first output transistor, a first regulated voltage that is based on the first reference voltage. The voltage multiplier circuit generates a second reference voltage from an equivalent of the first reference voltage. The second voltage regulator circuit generates, at a first terminal of a second output transistor, a second regulated voltage that is based on the second reference voltage. At least one terminal of the second output transistor is capacitively coupled to the first terminal of the first output transistor.

Abstract: An airbag apparatus connected with a battery includes activation circuits each of which has a squib and a high-side switching element, a safing switching element connected between the battery and the activation circuits, a safing switch control circuit controlling the safing switching element to provide a target voltage to the activation circuits, a terminal voltage acquiring circuit that acquires a terminal voltage of each squib, and a target voltage setting circuit that sets the target voltage. When a maximum-terminal voltage is lower than a reference voltage, the target voltage setting circuit sets the target voltage to be equal to the reference voltage. When the maximum-terminal voltage is higher than the reference voltage, the target voltage setting circuit sets the target voltage to correspond to the maximum-terminal voltage so that a reverse current is avoided in the high-side switching element.

Abstract: A method of provisioning an integrated circuit with decoupling capacitance includes identifying in an initial design of the integrated circuit lacking decoupling elements, a standard cell instance satisfying a transient power or frequency switching criteria. Based on a transient power characteristic of the standard cell instance, a decoupling capacitance requirement for the standard cell instance is determined. The decoupling capacitance requirement indicates a capacitance sufficient to bring the standard cell instance into compliance with a stability constraint on a supply voltage node of the standard cell instance. A decoupling capacitor satisfying the decoupling capacitance requirement is provisioned by appending an appropriate sized decap transistor having one or more gate electrode elements to the standard cell instance.

Abstract: A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current. A resistor is coupled between a node from the voltage controlled current source and a negative charge output from the negative charge pump. A capacitor is placed in parallel with the resistor. A comparator generates the pump enable signal to control the negative charge pump. The comparator is coupled to the resistor and the capacitor and measures an IR drop thereacross and compares this measurement against a reference threshold. A level of the pump enable signal can be variable by tuning an amount of resistance of the resistor or capacitor or adjusting the reference threshold. A memory can be driven by a method of the negative charge pump.

Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.

Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.

Abstract: A power source delivers power from a main power source using switching by a normally on transistor. A driver switches on and off the normally on transistor under a control signal by a controller during regular operation. A housekeeping power supply delivers auxiliary power to the driver. The driver switches off the normally on transistor during irregular operation. Irregular operation occurs at least when the control signal is absent or no auxiliary power is available or during transients such a power up or down. Bridge block pairs thereof can be arranged to form a half bridge power switch, an H bridge switch, a three phase bridge switch, a multi-phase switch, a buck converter, a buck-boost converter, or a boost converter.

Abstract: An angular rate sensor (20) includes a single drive mass (24) and distributed sense masses (36, 38, 40, 42) located within a central opening (30) of the drive mass (24). The drive mass (24) is enabled to rotate around the Z-axis (64) under electrostatic stimulus. The sense masses (36, 38, 40, 42) are coupled to the drive mass by spring elements (44, 46, 48, 50) such that oscillatory rotary motion (90) of the drive mass imparts a linear drive motion (92, 94) on the sense masses. The distributed sense masses form two pairs of sense masses, where one pair senses X- and Z-axis angular rate and the other pair senses Y- and Z-axis angular rate. The sense masses are coupled to one another via a centrally located coupler element (34) to ensure that the sense masses of each pair are moving in anti-phase.

Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming, a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

Abstract: A sensor system includes a microelectromechanical systems (MEMS) sensor, a processor, measurement circuitry, stimulus circuitry and memory. The MEMS sensor is configured to provide an output responsive to physical displacement within the MEMS sensor to the measurement circuitry. The stimulus circuitry is configured to provide a stimulus signal to the MEMS sensor to cause a physical displacement within the MEMS sensor. The measurement circuitry is configured to process the output from the MEMS sensor and provide it to the processor. The processor is configured to generate stimulus signals and provide them to the stimulus circuitry for provision to the MEMS sensor. The processor is configured to monitor the output from the measurement circuitry corresponding to the physical displacement occurring in the MEMS sensor, calculate MEMS sensor characteristics based on the output, and update calibration values based on the output. Methods for monitoring and calibrating MEMS sensors are also provided.

Abstract: A sensor system includes a microelectromechanical systems (MEMS) sensor, processing circuitry, measurement circuitry, stimulus circuitry and memory. The system is configured to provide an output responsive to physical displacement within the MEMS sensor to the measurement circuitry. The stimulus circuitry is configured to provide a stimulus signal to the MEMS sensor to cause a physical displacement within the MEMS sensor. The measurement circuitry is configured to process the output from the MEMS sensor and provide it to the processing circuitry, which is configured to generate stimulus signals and provide them to the stimulus circuitry for provision to the MEMS sensor. Output from the measurement circuitry corresponding to the physical displacement occurring in the MEMS sensor is monitored and used to calculate MEMS sensor characteristics. Methods for monitoring and calibrating MEMS sensors are also provided.