Abstract: A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first plurality of write ports, a write select signal coupled to the write ports, a plurality of write port address lines coupled as input to each of the write ports, and a first plurality of word line select circuits coupled to receive an address signal and the write select signal for each of the write ports and to provide a single selected write word line signal to a respective one of the rows of the storage devices for one of the first plurality of write ports activated by the write select signal.

Abstract: A packaged semiconductor device includes a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die.

Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.

Abstract: Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Abstract: Embodiments of a semiconductor device include a primary portion of a substrate, a die, and a die attach layer between the die and the primary portion of the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Abstract: An electromagnetic band gap device is provided, comprising: a conductive plane; a non-conductive substrate located over the conductive plane; and an electromagnetic band gap unit cell that includes a first via located in the non-conductive substrate and filled with a conductive material, a second via located in the non-conductive substrate and filled with the conductive material, a first conductive surface located on the non-conductive substrate over the first via, and a second conductive surface located on the non-conductive substrate over the second via, wherein the electromagnetic band gap unit cell is configured to operate as an LC resonant circuit in conjunction with the conductive plane, at least one gap is located in the electromagnetic band gap unit cell, the at least one gap being located in the first via, in the first conductive surface, in the second conductive surface, and in the second via.

Abstract: Systems and methods are provided for monitoring operation of MEMS accelerometers (100). In these embodiments a control loop (112) having a forward path (114) is coupled a MEMS transducer (110), and a test signal generator (124) and test signal detector (126) is provided. The test signal generator (124) is configured to generate a test signal and apply the test signal to the forward path (114) of the control loop (112) during operation of the MEMS accelerometer transducer (110). The test signal detector (126) is configured to receive an output signal from the control loop and detect the effects of the test signal in the output signal. Finally, the test signal detector (126) is further configured to generate a monitor output indicative of the operation of the sensing device to provide for the continuous monitoring of the operation of the MEMS accelerometer (100).

Abstract: A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively.

Abstract: A clock signal generator module arranged to generate at least one clock signal for at least one functional module is described. The clock signal generator module comprises a first clock source component associated with at least one functional module, at least one further clock source component associated with the at least one functional module, and at least one management unit arranged to controllably enable signal generation by the first and at least one further clock source components in accordance with at least one operating characteristic of the at least one functional module associated therewith.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first series circuit and a second series circuit in parallel with the first series circuit. The first series circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first adjustable attenuator series coupled between the first input and the first output. The second series circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter and a second adjustable attenuator series coupled between the second input and the second output.

Abstract: Systems and methods are provided for improved multifunction sensing. In these embodiments a multifunction sensing device (100) includes a microelectromechanical (MEMS) gyroscope (110) and at least a second sensor (112). The MEMS gyroscope (110) is configured to generate a first clock signal, and the second sensor includes a second clock signal. The multifunction sensing device further includes a reset mechanism (114), the reset mechanism (114) configured to generate a reset signal to set the relative periodic phase alignment of the second clock signal to the first clock signal. Consistently setting the relative periodic phase alignment of the clocks for the other sensor devices (112) to the clock of the MEMS gyroscope (110) can improve the performance of the devices by reducing the probability that varying output offsets will occur in the multiple sensing devices.

Abstract: An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., 21, 31, 41, 51) with one or more operatively inert high-k metal gate transistors (e.g., HKMG PMOS 112) having switched or altered work function metal layers (82) where the security circuit defines a first electrical function with the one or more operatively inert high-k metal gate transistors and defines a second different electrical function if the one or more operatively inert high-k metal gate transistors were instead fabricated as operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer of the first polarity type, the security circuit would define a second different electrical function.

Abstract: A direct-sequence spread spectrum signal receiving device may comprise a receiver unit, a chip sequence generating unit, a correlation unit, and comparison unit. The receiver unit may extract a chip stream from a radio-frequency signal, said chip stream containing a first chip sequence. The chip sequence generating unit may generate a plurality of trial chip sequences on the basis of a first trial chip sequence and on the basis of a plurality of index rotations. The correlation unit may determine a plurality of correlation values on the basis of said plurality of trial chip sequences and on the basis of said first chip sequence, each of said correlation values indicating a degree of correlation between a respective one of said trial chip sequences and said first chip sequence. The comparison unit may determine whether a maximum one of said correlation values exceeds a defined threshold value.

Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.

Abstract: Systems and methods are provided for monitoring operation of MEMS gyroscopes (110). A test signal generator (124) is configured to generate and apply a test signal to the rate feedback loop (112) of a MEMS gyroscope (110). A test signal detector (126) is coupled to the quadrature feedback loop (114) of the MEMS gyroscope (110) and is configured to receive a quadrature output signal from the quadrature feedback loop (114). The test signal detector (126) demodulates the quadrature output signal to detect effects of the test signal. Finally, the test signal detector (126) is configured to generate a monitor output indicative of the operation of the sensing device based at least in part on the detected effects of the test signal in the quadrature output signal. Thus, the system is able to provide for the continuous monitoring of the operation of the MEMS gyroscope (110).

Abstract: A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.

Abstract: A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well.

Abstract: Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.

Abstract: Methods and receiver circuits are provided for correlating an incoming signal with PN codes. An embodiment of the method includes receiving I/Q baseband samples in the I/Q domain; converting the I/Q baseband samples to phase baseband samples; generating a pseudonoise (PN) code; converting the PN code to PN phase data; performing a correlation on the phase baseband samples using the PN phase data to generate correlated I/Q values; performing an adding operation on the correlated I/Q values to generate demodulated I/Q values; converting the demodulated I/Q values into demodulated phase values; performing a frequency correction operation on the demodulated phase values to generate frequency correction data; converting the demodulated I/Q values into demodulated magnitude values; and performing signal decoding and synchronization on the magnitude values to generate output data. The operation of performing correlation on the phase baseband samples using the PN phase data is accomplished using scalar subtraction.

Abstract: Test control point insertion and x-bounding for Logic Built-In Self-Test (LBIST) using observation circuitry. In some embodiments, LBIST circuitry may include a plurality of test control circuits coupled to a scan chain of a Circuit Under Test (CUT), and a plurality of observation circuits coupled to the test control circuits, each of the plurality of observation circuits including one or more latch devices configured to drive a respective one of the plurality of test control circuits. In other embodiments, a method of testing an integrated circuit may include issuing an instruction that a plurality of observation circuits and a plurality of input/output (I/O) control circuits within the integrated circuit enter a test mode, and providing, one or more test patterns to a selected one or more of a plurality of scan chains within the integrated circuit and to each of the plurality of observation circuits.