Abstract: A circuit for reducing peak power during transition fault testing of an integrated circuit (IC) includes a programmable register that receives scan shift and SDI (scan data in) signals. Input and output ports of the programmable register are connected together. A multiplexer is provided that has a first input port that is maintained asserted, and a second input port connected to the output port of the programmable register. A scan shift signal, which remains asserted during a scan shift operation and de-asserted during a scan capture operation, is provided at a select input port of the multiplexer. The output of the multiplexer is provided as an input to a clock gating cell. The clock gating cell selectively provides the clock signal to the scan-chain flip-flops in the IC based on the scan shift signal and a functional enable signal, and reduces peak power during transition fault testing.

Abstract: A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further comprises performing cell variant optimization comprising identifying at least one cell of the at least one cell type to be substituted and substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell. The method further comprises, during cell optimization, configuring a pin interconnect modification for mapping at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout.

Abstract: A sense amplifier (100) includes first and second inverters (112 and 113). The first inverter has an input terminal (116) and an OUT_B output node and a first transistor (124). The second inverter (113) has an input terminal (115) and an OUT output node and a second transistor (125). The OUT_B output node of the first inverter is coupled to an input terminal of the second inverter, and the OUT node of the second inverter is coupled to an input terminal of the first inverter. The sense amplifier does not use a reference current; therefore, the sense amplifier does not need a reference current generator. The sense amplifier needs only one enable signal to reset a latch (110) of the sense amplifier. When coupled to a non-volatile memory element, voltages at the output nodes are indicative of a logic level of a bit stored in the non-volatile memory element.

Abstract: A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.

Abstract: A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (NVM) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted. In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted. In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle, whether the maximum number of the soft program pulses has exceeded a predetermined threshold, whether the number of erase pulses has increased comparing to a previous erase cycle, or combinations thereof. In response to such determinations, the NVM is either passed or failed on the basis of the absence or presence of a slow bit in the NVM.

Abstract: A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit.

Abstract: A programmable clock divider includes first and second comparators for generating first and second signals respectively based on a count value of a counter and a frequency ratio value. First and second flip-flops delay the first and second signals by one clock cycle of the input clock signal. An active-low latch delays the second signal by half a clock cycle of the input clock signal. A multiplexer receives the delayed first and second signals at first and second input terminals respectively and the input clock signal at a select terminal, and generates a divided clock signal. The multiplexer outputs the second delayed signal when the input clock signal is at a logic high state and outputs the first delayed signal when the input clock signal is at a logic low state.

Abstract: An oscillator circuit includes a charge current source and first and second muxes. The first mux has a common node, a discharge node, a control node and a charge node coupled to the charge current source. The control node couples the common node to either the discharge or charge nodes. The second mux has a shared node, a reference node, a control node and a ground node coupled to ground. The second mux control node couples the shared node to either the reference or ground nodes. A capacitor is coupled between the common node and the shared node. A comparator has a non-inverting input coupled to the common node, an inverting input coupled to the reference node, and an output coupled to the first and second control nodes. A discharge current sink couples the discharge node to ground and an oscillator output is provided by the comparator.

Abstract: Methods and apparatus are provided for an electronic panel assembly (EPA) (82, 83), comprising: providing one or more electronic devices (30) with primary faces (31) having electrical contacts (36), opposed rear faces (33) and edges (32) therebetween. The devices (30) are mounted primary faces (31) down on a temporary support (60) in openings (44) in a warp control sheet (WCS) (40) attached to the support (60). Plastic encapsulation (50) is formed at least between lateral edges (32, 43) of the devices (30) and WCS openings (44). Undesirable panel warping (76) during encapsulation is mitigated by choosing the WCS coefficient of thermal expansion (CTE) to be less than the encapsulation CTE. After encapsulation cure, the EPA (82) containing the devices (30) and the WCS (40) is separated from the temporary support (60) and, optionally, mounted on another carrier (70) with electrical contacts (36) exposed.

Abstract: A mechanism for determining cumulative process-induced damage due to the antenna effect during formation of an integrated circuit is provided. This cumulative process-induced damage is compared to a cumulative process-induced damage threshold for each layer to determine whether a violation has occurred, or whether cumulative damage below a threshold is such that a more aggressive use of conductive material in a subsequently formed layer can be made. The cumulative damage can also be compared to a cumulative process-induced damage warning threshold at each layer in order to warn a designer that steps should be taken during design/formation of subsequent conductive layers to reduce the cumulative damage. In addition, automated solutions are provided for exceeding either threshold, such as connecting conductive layers at a later stage in processing to avoid charge buildup on the gate dielectric or inclusion of diode devices to leak charge from the interconnect layers.

Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.

Abstract: A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current. A resistor is coupled between a node from the voltage controlled current source and a negative charge output from the negative charge pump. A capacitor is placed in parallel with the resistor. A comparator generates the pump enable signal to control the negative charge pump. The comparator is coupled to the resistor and the capacitor and measures an IR drop thereacross and compares this measurement against a reference threshold. A level of the pump enable signal can be variable by tuning an amount of resistance of the resistor or capacitor or adjusting the reference threshold. A memory can be driven by a method of the negative charge pump.

Abstract: A multi-level clock signal distribution network comprises a plurality of lower network levels comprising at least a first lower network level and a lowermost network level that is connected to one or more lowermost clock signal driving circuits connectable to receive a clock signal; and a topmost network level arranged to distribute the clock signal to a plurality of clocked circuits, and connected to a plurality of topmost clock signal driving circuits connected to receive the clock signal from the first lower network level. The lowermost network level comprises at least one net and each of the plurality of lower network levels except the lowermost network level comprises a plurality of nets and is connected to a corresponding plurality of lower clock signal driving circuits being connected to receive the clock signal from a subjacent one of the plurality of lower network levels, wherein each of the plurality of nets is driven by all nets of the subjacent one.

Abstract: A method for producing a verified design of a digital to analog converter (DAC) starts with providing an HDL representation of the DAC. Numerical values of the analog output signal as a function of the representation of the DAC for a range of numerical values of the digital input signal are simulated with a simulator. A model is used for converting the simulated numerical values of the analog output signal to numerical values of an equivalent model signal in the same digital format as the input signal. A comparator compares the numerical values of the input signal and the model signal and determines differences greater than a defined tolerance.

Abstract: Embodiments of a method for fabricating Redistributed Chip Packages are provided, as are embodiments of Redistributed Chip Packages. In one embodiment, the method includes the steps/processes of embedding a first semiconductor die and a microelectronic component in a molded panel having a frontside, the first semiconductor die comprising a plurality of bond pads over which a plurality of raised contacts has been formed. The frontside of the molded panel is polished to impart the molded panel with a substantially planar surface through which the terminals of the microelectronic component and the plurality of raised contacts are exposed. Finally, at least one redistribution layer is build or produced over the substantially planar surface to electrically interconnect the first semiconductor die and the microelectronic component.

Abstract: A power control circuit includes a plurality of transistors coupled between a power supply node and a gated power supply node, wherein the gate electrode of a first transistor of the plurality of transistors is coupled to receive a power control signal, wherein, in response to assertion of the power control signal, the first transistor is placed into a conductive state; a first voltage comparator, wherein, in response to assertion of the power control signal, places a second transistor of the plurality of transistors in a conductive state when a voltage on the gated voltage supply node reaches a first reference voltage; and a second voltage comparator, wherein, in response to assertion of the power control signal, places a third transistor of the plurality of transistors in a conductive state when the voltage on the gated voltage supply node reaches a second reference voltage different from the first reference voltage.

Abstract: Embodiments of information processing systems and associated components can include logic operable to perform operations in a virtualized system including a plurality of guest operating systems using descriptors. The descriptors specify a set of commands defining the operations in a plurality of security domains and specify permission to a plurality of resources selectively for the plurality of guest operating systems.

Abstract: In accordance with at least one embodiment, an improved voltage headroom self-biased receiver is provided. In accordance with at least one embodiment, tail current sources are biased so as to be cross-coupled with respect to each other. In accordance with at least one embodiment, startup control is provided to counter defect-induced current and to ensure the circuit can function properly even with large amounts of defect current. In accordance with at least one embodiment, a positive type (p type) channel metal oxide semiconductor (PMOS) tail current transistor is modulated by a negative type (n type) channel metal oxide semiconductor (NMOS) differential pair virtual negative supply voltage and a NMOS tail current transistor is modulated by a PMOS differential pair virtual positive supply voltage. The amplifier's output common mode is thus self correcting to p type to n type transistor strength differences.

Abstract: A fault diagnostic circuit (100) and associated method of operation are described for testing an FET device (114) for a gate-drain short failure (113) by floating the FET gate during a predetermined test period and then comparing (118) the FET output voltage (115) at the source to a predetermined threshold voltage (VTHRESHOLD) which may be selected as a percentage of the power supply voltage (VPOWER) for the FET device to determine if the FET output voltage is greater than the threshold voltage, in which case a device fault is signaled (119).

Abstract: An adaptor for a solid-state oscillator and related microwave adaptors includes an input segment of a conductive material, a first coaxial portion that includes a first inner conductor coupled to the input segment and a first outer shielding segment, and a capping portion coupled to the first coaxial portion to electrically couple the first inner conductor and the first outer shielding segment.