Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.

Abstract: A circuit includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102) is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.

Abstract: A self-powered circuit package includes a substrate and an integrated circuit (IC). The IC is mounted on a surface of the substrate. An electrical interconnector electrically couples the IC to the substrate. A solar cell is provided having opposing first and second main surfaces. A portion of the first main surface of the solar cell is configured to receive light from an external source. The solar cell converts energy of the received light into electrical power. The solar cell is disposed above the IC and electrically connected to the IC by way of the substrate to supply the generated power to the IC. A clear mold compound encapsulates a surface of the substrate, the IC, the electrical interconnector, and the solar cell.

Abstract: A MEMS device (20) with stress isolation includes elements (28, 30, 32) formed in a first structural layer (24) and elements (68, 70) formed in a second structural layer (26), with the layer (26) being spaced apart from the first structural layer (24). Fabrication methodology (80) entails forming (92, 94, 104) junctions (72, 74) between the layers (24, 26). The junctions (72, 74) connect corresponding elements (30, 32) of the first layer (24) with elements (68, 70) of the second layer (26). The fabrication methodology (80) further entails releasing the structural layers (24, 26) from an underlying substrate (22) so that all of the elements (30, 32, 68, 70) are suspended above the substrate (22) of the MEMS device (20), wherein attachment of the elements (30, 32, 68, 70) with the substrate (22) occurs only at a central area (46) of the substrate (22).

Abstract: A data processing apparatus includes a processing unit for processing data, including receiving data packets from a sender and sending acknowledgements to the sender, the processing unit having a first and second mode of operation, the second mode of operation requires more power than the first mode, and the processing unit switches between the first and second modes of operation based on a processing load; a metric module for determining a metric indicative of the processing load; an acknowledgement module for sending one acknowledgement in respect of n received data packets; and an acknowledgement configuration module for setting n to be a value m greater than a first predetermined value if the metric lies in a predetermined range that includes a value that the metric assumes when the processing unit switches between the first mode of operation and the second mode of operation, and to the first predetermined value otherwise.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.

Abstract: A real-time distributed network slave module is described. The real-time distributed network slave module comprises a first communications component arranged to transmit and receive real-time distributed network data over at least a first real-time distributed network connection, at least one further communications component arranged to transmit and receive real-time distributed network data over at least one further real-time distributed network connection, and at least one processing component.

Abstract: A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells (110) prior to the formation of high-k metal gate electrodes for CMOS transistors (212, 213) using a planarized dielectric layer (26) and protective mask (28) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: Forming a packaged semiconductor device includes placing a semiconductor die attached to a carrier into a mold cavity having an injection port, wherein the semiconductor die has an encapsulant exclusion region on a top surface of the semiconductor die within an outer perimeter of the top surface; and flowing an encapsulant over the semiconductor die and carrier from the injection port, wherein the encapsulant flows around the encapsulant exclusion region to surround the encapsulant exclusion region without covering the encapsulant exclusion region. The encapsulant exclusion region has a first length corresponding to a single longest distance across the encapsulant exclusion region, wherein the first length is aligned, within 30 degrees, to a line defined by a shortest distance between an entry point of the injection port into the mold cavity and an outer perimeter of the encapsulant exclusion region.

Abstract: A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.

Abstract: A tone relay system comprises a tone detector arranged to receive a sequence of signal samples and to provide a plurality of media descriptors, each media descriptor comprising a cell of one or more of the signal samples and a tone detection meta-information for the cell; and a tone relay module arranged to receive each media descriptor, to perform an evaluation of the meta-information and modify the meta-information depending on one or more preceding media descriptors when a result of the evaluation indicates an undetermined tone state, and to provide the media descriptors with a predetermined delay to a tone aggregator module, when the meta-information indicates a tone, for transmission over a network, and to provide the media descriptors without the predetermined time delay to an encoder module, for transmission over the network, otherwise.

Abstract: A method and system for resolving a conflict between private internet protocol addresses assigned in a network between an internet protocol security remote access server (IRAS) and an internet protocol security remote access client (IRAC) arranged behind a network address translator (NAT) router in the network. By modifying internet key exchange version2 (IKEv2) and internet key exchange (IKE) protocol negotiations between IRAC and IRAS to include a private attribute used by IRAC to send all its internet protocol (IP) subnet addresses to IRAS, IRAS dynamically resolves any conflict of the IP addresses with that of its internal networks by mapping and assigning non-conflicting virtual IP addresses and network subnet addresses to IRAC for IRAC to access the internal networks of IRAS.

Abstract: An apparatus for detecting one or more predetermined tones transmitted over a communication network, each predetermined tone having a predetermined frequency, comprises a data memory for storing data including the predetermined frequency of each of the one or more predetermined tones, an input for receiving a signal transmitted over the communication network, and a frequency divider for dividing the received signal into at least two frequency sub bands so as to provide at least two components of the received signal in different frequency sub bands. The different frequency sub bands are selected based on the predetermined frequencies of the one or more predetermined tones.

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract: Forward bulk biasing circuitry for PMOS and NMOS transistors is provided. The bulk biasing circuitry includes two N-type MOS transistors, two P-type MOS transistors, and two capacitors. The forward bias to a bulk terminal of a transistor increases a threshold voltage of a transistor, thereby reducing a transition time and improving the performance of the transistor. The forward bias is provided only when the transistor transitions from one state to another, thereby reducing leakage power dissipation during active and standby modes of an integrated circuit that includes the transistor.

Abstract: A decoder for decoding a set of bits encoded using a Bose-Chaudhuri-Hocquenghem (BCH) error-correcting code (ECC) includes a syndrome generator, a key equation solver, and an error bit locator. The syndrome generator receives the set of encoded bits and generates a set of syndromes. The key equation solver generates an error location polynomial based on the set of syndromes. The error bit locator generates an error match bit using the error location polynomial, and the error match bit is used to identify and correct errors in the set of encoded bits.

Abstract: A method can include generating a first set of sample values for input variables in accordance with a prescribed set of probability distributions, running a set of simulations on an electronic component based upon the first set of sample values, multiplying the standard deviations of the original distributions by a scaling factor ?, generating a second set of sample values for the input variables based on the probability distributions thus generated, and running a set of simulations on the electronic component based on this second set of sample values. The method can also include the generation of Q-Q plots based on the data from the first and second set of simulations and data from a truly normal distribution or the distribution obeyed by the independently varying input parameters; and the use of these plots for assessment of the robustness and functionality of the electronic component.

Abstract: A memory device that accurately tracks memory operations includes a vertical loopback for tracking a sense clock signal to a row address decoder, and read and write reference bit lines in a reference column that include loopbacks for vertically tracking a selected bit line during read and write operations. Preferably the widths of word lines and a sense line are equal to enable the sense line to horizontally track any selected word line. The memory device also includes tri-state input/output (I/O) latches to latch sense amplifier outputs. A drive circuit of the tri-state I/O latch is disabled when the output is available at the corresponding sense amplifier and enabled when the output is latched by the latch circuit.

Abstract: An electronic device including a nonvolatile memory cell can include a substrate including a first portion and a second portion, wherein a first major surface within the first portion lies at an elevation lower than a second major surface within the second portion. The electronic device can also include a charge storage stack overlying the first portion, wherein the charge storage stack includes discontinuous storage elements. The electronic device can further include a control gate electrode overlying the first portion, and a select gate electrode overlying the second portion, wherein the select gate electrode includes a sidewall spacer. In a particular embodiment, a process can be used to form the charge storage stack and control gate electrode. A semiconductor layer can be formed after the charge storage stack and control gate electrode are formed to achieve the substrate with different major surfaces at different elevations. The select gate electrode can be formed over the semiconductor layer.

Abstract: Embodiments of systems and methods for detecting errors that occur in association with an access to a memory and providing an associated error status are presented herein. According to one embodiment, an access to a memory may be received, where the access comprises a request tag. A request parity is determined based on the request tag and a stored tag and a stored parity associated with the request tag are also determined. An error correction status is determined based on the stored tag and the stored parity associated with the request tag. Additionally, a parity hotness is determined by comparing the request parity and the stored parity and a tag hotness is determined by comparing the request tag and the stored tag. An error status associated with the access is determined based on the parity hotness, the tag hotness and the error correction status.