Abstract: A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.

Abstract: An adaptor for a solid-state oscillator and related microwave adaptors includes an input segment of a conductive material, a first coaxial portion that includes a first inner conductor coupled to the input segment and a first outer shielding segment, and a capping portion coupled to the first coaxial portion to electrically couple the first inner conductor and the first outer shielding segment.

Abstract: Systems and methods for transition control in a hybrid Switched-Mode Power Supply (SMPS). In some embodiments, a hybrid SMPS may include linear circuitry configured to produce an output voltage proportional to a variable duty cycle when the SMPS operates in linear mode and hysteretic circuitry coupled to the linear circuitry, the hysteretic circuitry configured to cause the duty cycle to assume one of two predetermined values when the SMPS operates in hysteretic mode. The hybrid SMPS may also include transition circuitry coupled to the linear circuitry and to the hysteretic circuitry, the transition circuitry configured to bypass at least a portion of the linear circuitry in response to the hybrid SMPS transitioning from the hysteretic mode to the linear mode.

Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.

Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.

Abstract: A brownout tolerant EEPROM emulator (18) manages memory operations at a volatile memory (20) and non-volatile memory (24) using a plurality of sector status bits (451) and forward/reverse skip flags (452, 453) stored in a sector identification record (45) of each sector to define a plurality of status indicators arranged sequentially to specify a plurality of sector configuration states for each memory sector, and to automatically bypass one or more dead sectors in the non-volatile memory array during forward copydown and reverse search operations.

Abstract: A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

Abstract: A state retention power gated (SRPG) cell includes an input control circuit having an input coupled to an input signal and an output. The input control circuit includes has transistors configured as a first inverter transmission gate. The transistors also connect in series at least one transistor controlled by a power gating signal. A first latch has an input coupled to the output of the input control circuit and an output. A transmission gate has an input coupled to the output of the first latch and an output that is an output of the SRPG cell. A second latch has an input coupled to the output of the transmission gate and an output that also is an output of the SRPG cell. A second inverter transmission gate has an input coupled to the output of the second latch.

Abstract: A system and method of calibrating an amplifier are presented. The amplifier has a first amplification path and a second amplification path. A first state of the amplifier is identified defining a first phase shift of the first path and a second phase shift of the second path resulting in a maximum efficiency of the amplifier when an attenuation of the first path and an attenuation of the second path are set to first attenuation values. The attenuation of the first path and the attenuation of the second path is set to achieve a maximum efficiency of the amplifier when the phase shift of the first path and the phase shift of the second path are set according to the first state.

Abstract: Apparatus and systems are provided for a single amplifier filter capable of a high quality factor. A filter comprises an amplifier having an amplifier input and an amplifier output, wherein the amplifier is configured to produce an output signal at the amplifier output based on a signal at the amplifier input. A first resistive element is coupled between an input node and the amplifier input, a second resistive element is coupled between a first node and the amplifier input, and a third resistive element is coupled between the amplifier output and the first node. A first capacitive element is coupled between the amplifier output and the amplifier input. The filter comprises a second node for an inverse of the output signal, wherein a second capacitive element is coupled between the first node and the second node.

Abstract: Apparatus, systems, and fabrication methods are provided for biasing amplifier arrangements inside device packages to a target quiescent current. In one embodiment, an amplifier device has an output interface and includes an amplifier arrangement having an amplifier output and impedance matching circuitry coupled between the amplifier output and the output interface. A method for biasing the amplifier arrangement involves measuring or otherwise obtaining a voltage between the amplifier output and the output interface, determining an estimated quiescent current through the amplifier arrangement based on that voltage, and adjusting a bias voltage provided to the input of the amplifier arrangement based on a difference between the estimated quiescent current. In exemplary embodiments, the bias voltage is adjusted until the estimated quiescent current is substantially equal to a target quiescent current.

Abstract: A voltage controlled oscillator includes a plurality of serially connected composite gain stages. A composite gain stage includes a transconductance stage and a transimpedance stage. The transconductance stage has first and second current paths from a first power supply voltage terminal to a second power supply voltage terminal. A first variable resistance is coupled between the first and second current paths. The transimpedance stage has a first inverter and a second inverter. The first inverter has an input terminal coupled to the output of the first current path and an output terminal. The second inverter has an input terminal coupled to the output of the second current path, and an output terminal. A second variable resistance is coupled between the input terminal and the output terminal of the first inverter, and a third variable resistance is coupled between the input terminal and the output terminal of the second inverter.

Abstract: An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.

Abstract: A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled to the precharge circuit that enables the precharge circuit at a beginning portion of a read cycle, keeps the precharge circuit disabled until an end of the read cycle, and keeps the precharge circuit disabled during a write cycle. A method of operating a memory, in which the memory includes an array of memory cells coupled to bit lines, includes precharging the bit lines at a beginning of a read cycle. The method also includes blocking precharging of the bit lines for a duration of a write cycle.

Abstract: A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.

Abstract: A real-time distributed network module arranged to provide an interface between at least one master application and at least one real-time distributed network. The real-time distributed network module comprises a first communications component arranged to transmit and receive real-time distributed network data over at least a first real-time distributed network connection, at least one further communications component arranged to transmit and receive real-time distributed network data over at least one further real-time distributed network connection at least one master application interface component arranged to provide an interface to the at least one master application, and at least one configuration component arranged to perform mapping of communication channels between the first communications component, the at least one further communications component and the at least one master application interface component.

Abstract: A receiver circuit, comprises an input balun circuit comprising a balanced balun output and being capable of receiving RF signals, an input amplification circuit comprising a balanced amplifier input and a balanced amplifier output, a single balanced in-phase mixing circuit comprising a first unbalanced RF mixer input and a balanced in-phase mixing frequency input, and a single balanced quadrature mixing circuit comprising a second unbalanced RF mixer input and a balanced quadrature mixing frequency input. The balanced amplifier input is connected to the balanced balun output, a first terminal of the balanced amplifier output is connected to provide an amplified RF signal to the first unbalanced RF mixer input and a second terminal of the balanced amplifier output is connected to provide a phase-shifted amplified RF signal to the second unbalanced RF mixer input.

Abstract: A battery equalization circuit is provided, comprising: a positive battery node connected to a positive terminal of a monitored battery cell contained in a battery circuit that includes a plurality of other battery cells connected in series with the monitored battery cell; a negative battery node connected to a negative terminal of the monitored battery cell; a secondary transformer coil configured to receive a square wave, the secondary transformer coil having an upper transformer node and a lower transformer node; an upper switch connected between the positive battery node and the upper transformer node; a lower switch connected between the negative battery node and the lower transformer control node; and a control circuit configured to control operation of the upper and lower switches based on a measured cell voltage between the positive battery node and the negative battery node, and a total battery voltage of the battery circuit.

Abstract: A battery equalization circuit is provided, including: a positive battery node connecting to a positive node of a battery cell in a battery circuit with a plurality of other battery cells; a negative battery node connected to a negative node of the battery cell; a transformer winding receiving an AC voltage, the transformer winding having an upper transformer node and a tower transformer node; an upper triac connected between the positive battery node and the upper transformer node; a lower triac connected between the negative battery node and the lower transformer node; a control circuit for controlling the upper triac and the lower triac based on a measured cell voltage between the positive battery node and the negative battery node, and a total battery voltage of the battery circuit; and an isolation element connected between the control circuit and a data bus.

Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.