Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.

Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.

Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.

Abstract: Adaptive error correction for non-volatile memories is disclosed that dynamically adjusts sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The adaptive error correction can also be used with respect to memories that are not non-volatile memories.

Abstract: A processing resource apparatus comprises a reference processing module comprising a set of reference stateful elements and a target processing module comprising a set of target stateful elements. A scan chain having a first mode for supporting manufacture testing is also provided, the scan chain being arranged to couple the reference processing module to the target processing module. The scan chain also has a second mode capable of synchronizing the set of target stateful elements with the set of reference stateful elements in response to a synchronization signal.

Abstract: A sigma delta modulator includes a first circuit that receives an analog signal and provides an intermediate signal and a first quantizer signal and further includes a first quantizer that receives the first quantizer signal and provides a first quantizer output. Also included are a second input circuit that receives the intermediate signal and provides a second quantizer signal and a second quantizer that receives the second quantizer signal and provides a second quantizer output. The first quantizer includes a programmable circuit having a first reference and a negative of the first reference, a first comparator having a first input coupled to the first quantizer signal, a second input coupled to the first reference and a second comparator having a second input coupled to the first quantizer signal a second input coupled to the negative. The first and second comparators have outputs that form the output of the first quantizer.

Abstract: Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.

Abstract: Embodiments include methods for securely provisioning copies of an electronic circuit. A first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the electronic circuit. A second entity (e.g., an OEM): 1) embeds a trust anchor in a first copy of the electronic circuit; 2) causes the electronic circuit to generate a message signing key pair using the trust anchor and the embedded secret value(s); 3) signs provisioning code using a code signing private key; and 4) sends a corresponding code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second copy of the electronic circuit and causes the electronic circuit to: 1) generate the message signing private key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code on the electronic circuit.

Abstract: A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.

Abstract: Methods and systems are provided for performing sampling sequences using a control module. One exemplary method involves transferring sampling configuration information for a sampling sequence from memory to a conversion module. The conversion module performs the sequence in accordance with the configuration information by performing sampling processes at a plurality of sampling times to obtain a plurality of samples, and transferring results corresponding to the plurality of samples from the conversion module to the memory. At least some sampling times of the plurality of sampling times are nonperiodic with respect to the other sampling times of the plurality of sampling times. In exemplary embodiments, the sampling configuration information includes a sampling mode criterion, and the conversion module either automatically performs a sampling process or performs the sampling process in response to a trigger signal based on the sampling mode criterion for that sampling process.

Abstract: A data processing system comprises a task scheduling device arranged to schedule a plurality of tasks; and a plurality of processing units, at least some of which being adapted to execute one or more assigned tasks of the plurality of tasks and, for each assigned task, to provide to the task scheduling device at least a task status event which indicates when an execution of the assigned task is finished; wherein the task scheduling device comprises a task scheduler controller unit arranged to assign one or more of the plurality of tasks, each to a corresponding one of the processing units being adapted to execute the assigned task, in response to receiving one or more of the task status events associated with one or more previously assigned tasks.

Abstract: An apparatus is provided. The apparatus includes a flip-flop including an input configured to receive a setup time and delay control (SDC) signal, and an output buffer including first and second conductive paths. The second conductive path is non-conductive when the SDC signal has a first value at the input and is conductive when the SDC signal has a second value at the input. The apparatus includes a propagation delay sensor configured to estimate a propagation delay of the flip-flop, and, when the estimated propagation delay exceeds a threshold, supply the SDC signal having the second value to the input of the flip-flop.

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

Abstract: A signal transmission system (10) includes a signal generator circuit (12); a signal regenerator circuit (14) coupled to the signal generator circuit by conductive lines (16, 18). The signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and the regenerator circuit includes cascoded transistors (39, 41) and level-shifting circuits (26) coupled to the cascoded transistors. The cascoded transistors amplify the input signals to provide amplified signals. The level-shifting circuits shift a voltage level of the amplified signals to provide level-shifted signals.

Abstract: An error detection system employs a chain of delay elements connected in an open loop configuration. To determine whether the oscillator is operating within a specified set of parameters, the error detection system applies a start pulse to an input of the open-loop chain of delay elements. The error detection system compares the resulting output signal with the output of the oscillator. If the oscillator has locked onto a harmonic of the intended output frequency, the comparison of the output signals will indicate an error.

Abstract: A technique for detecting in-band signaling tones in a communication system includes performing a first adaptation of an adaptive filter of an echo canceller in response to detection of a far-end harmonic signal. In this case, the adaptive filter provides an echo estimation signal. The technique also includes subtracting the echo estimation signal from a near-end signal that includes one or more in-band signaling tones to provide an error signal. The technique further includes detecting, using a tone detector, the one or more in-band signaling tones in the error signal.

Abstract: A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the first control node and a first current output node or between the second control node and a second current output node, and an activation current source provides activation current to the buffer circuit via the first and second control nodes. The master replica bias network replicates biasing of the buffer circuit relative to a replica control node and drives the buffer circuit to maintain the first control node, the second control node and the replica control node at a common master control voltage.

Abstract: A microelectronic assembly (100) and a microelectronic device (4100) include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.

Abstract: Reducing output voltage ripple of power supplies. In some embodiments, an electronic circuit may include a first node configured to receive an input signal proportional to an output voltage produced by a power supply, a second node configured to receive a reference voltage configured to alternate between two voltage values during operation of the power supply, and a third node configured to output an enabling signal configured to control the operation of the power supply in response to a comparison between the input signal and the reference voltage. In other embodiments, a method may include turning on a power supply in response to a falling ripple being smaller than a first reference voltage value, and turning off the power supply in response to a rising ripple being greater than a second reference voltage value, where the second reference voltage value is smaller than the first reference voltage value.

Abstract: An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.