Abstract: A memory system includes a memory and a content addressable memory (CAM). The memory includes a plurality of address locations, wherein each address location configured to store data and one or more error correction bits corresponding to the data. The CAM includes a plurality of entries, wherein each entry configured to store an address value of an address location of the memory and one or more extended error correction bits corresponding to the data stored at the address location of the memory.

Abstract: An integrated circuit package for sensing fluid properties includes: a substrate made of semiconductor material; a fluid property measurement circuit formed on the substrate; and a sensor circuit coupled to the fluid property measurement circuit within a same integrated circuit package. The sensor circuit is configured to generate a field that interacts with the fluid. The fluid property measurement circuit is configured to determine a change in a property of the sensor circuit as results from the field interacting with the fluid and is further configured to determine a property of the fluid based on the change in the property of the sensor circuit.

Abstract: An integrated circuit probing structure (40) is provided for evaluating functional circuitry (42), such as a slow slew-rate square wave signal from a low power circuit, where the probing structure includes two or more probe pads (48, 49) for testing the functional circuitry which are formed to be electrically separate from one another, and a probe test circuit (46) connected to the functional circuitry (42) for conveying a signal from the functional circuitry to a probe needle (47) only when the probe needle (47) electrically connects the two or more probe pads (48, 49).

Abstract: A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.

Abstract: A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Abstract: Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).

Abstract: A self-powered integrated circuit (IC) device includes a lead frame and a solar cell having first and second main surfaces. The solar cell is mounted on a surface of the lead frame. An IC chip is also provided. A first electrical interconnector electrically couples the IC chip to the lead frame and a second electrical interconnector electrically couples the solar cell to the IC chip. A portion of the first main surface of the solar cell is configured to receive light from an external source. The solar cell converts energy of the received light into electrical power that is supplied to the IC chip. A mold compound encapsulates the IC chip, the first and second electrical interconnectors, and at least a portion of the solar cell.

Abstract: A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.

Abstract: A transistor power switch device comprising an array of vertical transistor elements for carrying current between first and second faces of a semiconductor body. The device also comprises a semiconductor monitor element comprising first and second semiconductor monitor regions in the semiconductor body and a monitor conductive layer distinct from the current carrying conductive layer of the transistor array. The semiconductor monitor element presents semiconductor properties representative of the transistor array. Characteristics of the semiconductor monitor element are measured as representative of characteristics of the transistor array. Source metal ageing of a transistor power switch device is monitored by measuring and recording a parameter which is a function of a sheet resistance of the monitor conductive layer when the transistor power switch device is new and comparing it with its value after operation of the device.

Abstract: A datagram flow optimizer apparatus comprises a buffer resource capable of receiving and temporarily storing a plurality of datagrams in respect of a forward path. The apparatus also comprises and a buffer controller arranged to implement, when in use, buffering of received datagrams by the buffer resource until a predetermined threshold number of datagrams has been stored by the buffer resource. The apparatus further comprises an acknowledgement regulator arranged to use the buffer resource to manipulate temporal spacing between acknowledgements of datagrams on a reverse path. The buffer controller is arranged to permit forwarding on the forward path of datagrams stored by the buffer resource in response to the predetermined threshold number of stored datagrams being reached.

Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

Abstract: A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a second side of the thick die pad. A second lead frame of the dual gauge lead frame is provided. The second lead frame has thin lead fingers. One end of the lead fingers is attached to an active surface of the power die such that the lead fingers are electrically connected to bonding pads of the power die. A molding compound is then dispensed onto a top surface of the dual gauge lead frame such that the molding compound covers the power die and the lead fingers.

Abstract: An integrated circuit package comprising a substrate and at least one semiconductor die is described. A connection unit may provide electrical connections between the substrate and the semiconductor die. The connection unit may comprise a stack of conduction layers and isolation layers stacked atop each other. The stack may include a microstrip line or a coplanar waveguide. The microstrip line or the coplanar waveguide may be part of a balun, a power divider, or a directional coupler.

Abstract: An partially depleted Dieler LDMOSFET transistor (100) is provided which includes a substrate (150), a drift region (110) surrounding a drain region (128), a first well region (107) surrounding source region (127), a well buffer region (106) separating the drift region and first well region to at least partly define a first channel region, a gate electrode (118) formed over the first channel region having a source-side gate edge aligned with the first well region (107), an LDD extension region (120) extending from the source region to the channel region, and a dielectric RESURF drain extension structure (161) formed at the drain of the gate electrode (118) using the plurality of STI stripes (114).

Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.

Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.

Abstract: A rail to rail differential buffer input stage includes n-type and p-type input differential transistor pairs connected in voltage follower configuration to the power supply rails. A reference voltage generator includes a reference differential transistor pair generating a dynamic reference voltage relative to the common mode input voltage. Dummy n-type and p-type transistor pairs have current conducting paths connected in parallel with the input differential pairs and are controlled by the dynamic reference voltage to divert supply rail current away from and deactivate one of the associated input differential pairs when the common mode input voltage is further from the dynamic reference voltage than a threshold value. Both the dummy pairs conduct and both the input differential pairs are activated when the common mode input voltage is closer to the dynamic reference voltage VB than the threshold value so that the overall transconductance of the buffer input stage remains constant.

Abstract: A memory cell including a cross-coupled latch with corresponding storage nodes, and further including first and second write pass gate transistors and first and second read pass gate transistors. The write pass gate transistors are controlled by a write word line and the read pass transistors are controlled by a read word line. Each read and write pass gate transistor is coupled between a storage node and either a bit line or a complementary bit line. The write pass gate transistors are implemented at a first strength level and the read pass gate transistors are implemented at a second strength level which is less than the first strength level. In this manner, the read and write margins are independently configurable without negatively impacting each other.

Abstract: Each cache line of a cache has a lockout state that indicates whether an error has been detected for data accessed at the cache line, and also has a data validity state, which indicates whether the data stored at the cache line is representative of the current value of data stored at a corresponding memory location. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. In response to a cache invalidation event, the state of the lockout indicators for each cache line can be maintained so that locked out cache lines remain in the locked out state even after a cache invalidation. This allows memory error management software executing at the data processing device to robustly manage the state of the lockout indicators.

Abstract: A relaxation oscillator for generating an output clock signal includes a RC circuit, a bias generation stage, first and second comparator stages, and a logic circuit. The RC circuit generates first and second comparator input signals that are transmitted to the first and second comparator stages. The bias generation stage generates first and second bias voltages that are provided to each of the first and second comparator stages. The first and second comparator stages generate first and second comparator output signals, respectively, based on the first and second comparator input signals and the first and second bias voltages. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.