Abstract: A switching regulator includes a capacitor, a charge control circuit, a discharge detector, a switch circuit, and a feedback circuit. The charge control circuit charges and discharges the capacitor. The discharge detector has an input coupled to the capacitor to detect when the capacitor has discharged to a predetermined level to indicate an over-current condition. The switch circuit is coupled to receive an input voltage. The switch circuit is made conductive and non conductive by a switching signal for supplying an output voltage at a regulated voltage level. The duty cycle of the switching signal is reduced in response to an indication of an over-current condition. The feedback circuit is for controlling a discharge rate of the capacitor.

Abstract: A method includes generating a circuit design and executing a simulation of the circuit design at a plurality of time slices. Type 1 damage and type 2 damage are determined for each time slice. A total type 1 damage is provided as a sum of the type 1 damage for all of the slices in which type 1 damage is greater than type 2 damage. A total type 2 damage is similarly added for the slices where the type 2 damage is dominant. A type 1 aging effect is determined based on the total type 1 damage. A type 2 aging effect is determined based on the total type 2 damage. The type 1 aging effect is added to the type 2 aging effect to obtain a total aging effect. The circuit design is tested using the total aging effect to determine if the circuit design provides adequate lifetime performance.

Abstract: A multi-port memory cell of a multi-port memory array includes a first inverter that inverter is disabled by a first subset of write word lines and a second inverter, cross coupled with the first inverter, wherein the second inverter is disabled by a second subset of the plurality of write word lines. A first selection circuit has data inputs coupled to a first subset of a plurality of write bit lines, selection inputs coupled to the first subset of the plurality of write word lines, and an output coupled to the input of the second inverter. The second selection circuit has data inputs coupled to a second subset of the plurality of write bit lines, selection inputs coupled to the second subset of the plurality of write word lines, and an output coupled to the input of the first inverter.

Abstract: Embodiments of integrated circuits include a first input interconnect, a second input interconnect, an output interconnect, a shift register, a select register, a test access port (TAP) controller, and select register decode circuitry. The TAP controller is coupled to the first input interconnect and the select register, and the TAP controller is configured to shift a select value provided on the first input interconnect into the select register. The select register decode circuitry is configured to control, based on the select value, which of a plurality of test data output signals are provided to the output interconnect, where the plurality of test data output signals includes a first test data output signal and a second test data output signal. The first test data output signal is provided by the shift register, and the second test data output signal is received from a second integrated circuit on the second input interconnect.

Abstract: Silicon wafers and the like are cleaned using new scrubber-type apparatus in which measures are taken to compensate for differential cleaning of the central region of the wafer by: using rotary brushes having one or more non-contact portions arranged in the section thereof that faces the central region of the substrate, or toggling the relative position of the wafer and the rotary brushes, or directing cleaning fluid(s) preferentially towards the central region of the wafer. Another aspect of the invention provides scrubber-type cleaning apparatus in which the rotary brushes are replaced by rollers (110). A web of cleaning material (116) is interposed between each roller and the substrate. Various different webs of cleaning material may be used, e.g. a length of tissue, a continuous loop of cleaning material whose surface is reconditioned on each cleaning pass, adhesive material provided on a carrier tape, etc.

Abstract: A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. A method for forming the LDMOS transistor is also provided.

Abstract: A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value.

Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.

Abstract: Embodiments include methods for securely provisioning copies of an electronic circuit. A first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the electronic circuit. A second entity (e.g., an OEM): 1) embeds a trust anchor in a first copy of the electronic circuit; 2) causes the electronic circuit to generate a message signing key pair using the trust anchor and the embedded secret value(s); 3) signs provisioning code using a code signing private key; and 4) sends a corresponding code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second copy of the electronic circuit and causes the electronic circuit to: 1) generate the message signing private key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code on the electronic circuit.

Abstract: Embodiments of the present invention provide a voltage level shifter used to translate a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The input signal is provided by an input voltage varying between a first input voltage level and a second input voltage level. The output signal is provided by an output voltage varying between a first output voltage level and a second output voltage level. The output signal has a delay relative to the input signal, and the voltage level shifter has a leakage current. The voltage level shifter has a first operating mode and a second operating mode. In the second operating mode, the delay is shorter while the leakage current is higher than in the first operating mode.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first vertical drift region of semiconductor material, a second vertical drift region of semiconductor material, and a buried lateral drift region of semiconductor material that abuts the vertical drift regions. In one or more embodiments, the vertical drift regions and buried lateral drift region have the same conductivity type, wherein a body region of the opposite conductivity type overlies the buried lateral drift region between the vertical drift regions.

Abstract: A LIN network comprises a transmit driver for communicating on a single communication bus. A slope control module is operably coupled to a supply voltage and arranged to identify a voltage transition, and in response thereto and via control of the transmit driver selectively apply one of: a first voltage transition mode comprising a constant DV/DT slope transition, or a second voltage transition mode comprising a fixed time transition.

Abstract: A data processing system includes one or more processing unit arranged to execute sets of instructions stored in the data processing system. The sets may include two or more application sets, each forming an application sets and including instructions for scheduling for the application an event at a future point in time. The event may require the processing unit to be in an active mode. The sets may further include rescheduling instructions for receiving from the applications information about the scheduled events and determining whether or not one or more of the events can be rescheduled and rescheduling a reschedulable event to a new point in time. The sets may further include mode control instructions for controlling the processing unit to be in the active mode during a time interval which includes the new point in time and to be in a low power mode in which the processing unit consumes less energy than in the active mode during a period of time adjacent to the time interval.

Abstract: A semiconductor device includes a substrate on which an electronic circuit is provided. One or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an amount of a current flowing between the substrate and at least one of the at least one pad. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter.

Abstract: A technique for controlling transmit power of nodes in an ad-hoc network includes receiving, by a receiver of a leaf node included in the nodes of the ad-hoc network, a signal from a coordinator node included in the nodes of the ad-hoc network. The leaf node sets a transmit power of a transmitter of the leaf node based on a level of the signal and a desired minimum sensitivity for the receiver.

Abstract: A voltage supply circuitry is capable of coupling to wired audio headset circuitry and configurable to operate in a first mode, wherein the voltage supply circuitry provides a voltage supply to the wired audio headset functionality circuitry. The voltage supply circuitry is further capable of coupling to visual indication circuitry and further configurable to operate in a second mode, wherein the voltage supply circuitry provides a voltage supply to the visual indication circuitry.

Abstract: A device receives a request for an amount of a resource. It determines for each resource provider in a set of resource providers a current load, a requested load corresponding to the requested amount of the resource, and an additional load corresponding to an expected state of an application. It determines for each of the resource providers an expected total load on the basis of the current load, the requested load, and the additional load. It subsequently selects from the set of resource providers a preferred resource provider on the basis of the expected total loads. The resource may be one of the following: memory, processing time, data throughput, power, and usage of a device.

Abstract: The detector comprises a plurality of detection stages connected to a summator for providing a summation signal as a logarithmic representation of the input signal to a first input of a data slicer and an input of an average filter having an output connected to a second input of the data slicer. The data slicer has a data slicer output for providing an extracted digital data signal in dependence on a comparison of the summation signal and an output signal of the average filter. The average filter receives a first pre-charge voltage and a second pre-charge voltage depending on an output signal of a carrier detector circuit detecting a carrier signal of the input signal.

Abstract: An integrated circuit comprises trace logic for operably coupling to at least one memory element and for providing trace information for a signal processing system. The trace logic comprises trigger detection logic for detecting at least one trace trigger, memory access logic arranged to perform, upon detection of the at least one trace trigger, at least one read operation for at least one memory location of the at least one memory element associated with the at least one detected trigger, memory content message generation logic arranged to generate at least one memory content message comprising information relating to a result of the at least one read operation performed by the memory access logic, and output logic for outputting the at least one memory content message.

Abstract: A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.