Patents Assigned to Freescale
  • ELECTRONIC DEVICE AND A COMPUTER PROGRAM PRODUCT
    Publication number: 20140155027
    Abstract: An electronic device comprises a secured module arranged to store secured data. A component outside the secured module has a normal operating mode with a normal mode operating voltage. An interface is arranged to provide access to the secured module. A voltage monitoring unit is connected to the component and arranged to monitor an operating voltage Vsup of the component. An interface control unit is connected to the voltage monitoring unit and the interface. The interface control unit is arranged to inhibit access to the secured module through the interface when the operating voltage is below a predetermined secure access voltage level, the secure access voltage being higher than the normal mode operating voltage.
    Type: Application
    Filed: August 9, 2011
    Publication date: June 5, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Priel, Evgeny Margolis, Anton Rozen
  • INTEGRATED CIRCUIT DEVICE AND METHOD OF DYNAMICALLY MODIFYING AT LEAST ONE CHARACTERISTIC WITHIN A DIGITAL TO ANALOGUE CONVERTER MODULE
    Publication number: 20140152481
    Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.
    Type: Application
    Filed: July 20, 2011
    Publication date: June 5, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Stephane Dugalleix, Birama Goumballa, Gilles Montoriol
  • METHOD AND APPARATUS FOR ENABLING AN EXECUTED CONTROL FLOW PATH THROUGH COMPUTER PROGRAM CODE TO BE DETERMINED
    Publication number: 20140157240
    Abstract: A method of enabling an executed control flow path through computer program code to be determined. The method comprising modelling cumulative instruction counts for control flow paths through the computer program code, and inserting at least one probe within the computer program code to enable a cumulative instruction count value for at least one control flow path of the computer program code to be accessed.
    Type: Application
    Filed: July 20, 2011
    Publication date: June 5, 2014
    Applicant: Freescale Semiconductor, Inc
    Inventor: David Baca
  • System and method for efficient image feature extraction
    Patent number: 8744190
    Abstract: A system for efficient image feature extraction comprises a buffer for storing a slice of at least n lines of gradient direction pixel values of a directional gradient image. The buffer has an input for receiving the first plurality n of lines and an output for providing a second plurality m of columns of gradient direction pixel values of the slice to an input of a score network, which comprises comparators for comparing the gradient direction pixel values of the second plurality of columns with corresponding reference values of a reference directional gradient pattern of a shape and adders for providing partial scores depending on output values of the comparators to score network outputs which are coupled to corresponding inputs of an accumulation network having an output for providing a final score depending on the partial scores.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Norbert Stoeffler, Martin Raubuch
  • Inertial sensor with off-axis spring system
    Patent number: 8739627
    Abstract: An inertial sensor (20) includes a drive mass (30) configured to undergo oscillatory motion and a sense mass (32) linked to the drive mass (30). On-axis torsion springs (58) are coupled to the sense mass (32), the on-axis torsion springs (58) being co-located with an axis of rotation (22). The inertial sensor (20) further includes an off-axis spring system (60). The off-axis spring system (60) includes off-axis springs (68, 70, 72, 74), each having a connection interface (76) coupled to the sense mass (32) at a location on the sense mass (32) that is displaced away from the axis of rotation (22). Together, the on-axis torsion springs (58) and the off-axis spring system (60) enable the sense mass (32) to oscillate out of plane about the axis of rotation (22) at a sense frequency that substantially matches a drive frequency of the drive mass (30).
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gary G. Li, Yizhen Lin, Andrew C. McNeil, Lisa Z. Zhang
  • Sharing stacked BJT clamps for system level ESD protection
    Patent number: 8743516
    Abstract: An area-efficient, high voltage, dual polarity ESD protection device (200) is provided for protecting multiple pins (30, 40) against ESD events by using a plurality of stacked NPN devices (38, 48, 39) which have separately controllable breakdown voltages and which share one or common NPN devices (39), thereby reducing the footprint of the high voltage ESD protection circuits without reducing robustness and functionality.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chai Ean Gill, Rouying Zhan
  • Integrated assist features for epitaxial growth
    Patent number: 8741743
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
  • Identification mechanism for semiconductor device die
    Patent number: 8742599
    Abstract: A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Colby G. Rampley, Lawrence S. Klingbeil
  • Clocked memory with word line activation during a first portion of the clock cycle
    Patent number: 8743651
    Abstract: A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hema Ramamurthy, Ravindraraj Ramaraju
  • Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique
    Patent number: 8741719
    Abstract: A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Low power, high resolution timing generator for ultra-wide bandwidth communication systems
    Patent number: 8743927
    Abstract: A data communication method is provided, comprising: processing high-speed digital data for communication to produce processed data; generating short impulse wavelets; constructing a digitally modulated ultra wideband signal from the short impulse wavelets in response to bits of the processed data, wherein the digitally modulated ultra wideband signal comprises a series of the short impulse wavelets, and the value of each bit of the processed data is digitally modulated onto the shape of at least one of the short impulse wavelets of the series, to produce a series of digitally shape modulated impulse wavelets; and transmitting the digitally modulated ultra wideband signal, including the series of digitally shape modulated impulse wavelets, via an antenna.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: John W. McCorkle
  • High speed overlay mode for burst data and real time streaming (audio) applications
    Patent number: 8743862
    Abstract: In a wireless 802.15.4 communication system (300), a high-speed data frame structure (340) is provided which uses the 802.15.4 SHR structure that is spread modulated to obtain the synchronization benefits of the 802.15.4 protocol, but which uses a modified data frame structure for the payload portion without using spreading to thereby improve its transmission efficiency. The transmission efficiency can be further increased by increasing the size of the data payload (and correspondingly, the frame length size).
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Clinton C Powell, Kuor-Hsin Chang, Bing Xu
  • Semiconductor processing method
    Patent number: 8741071
    Abstract: A process for treating the surface of a substrate in the manufacture of a semiconductor device. The process comprises providing a concentrated acid or base, a peroxide and water, and delivering the acid or base, the peroxide and the water to the surface of the substrate. The acid or base and the water are delivered separately to the surface of the substrate and allowed to mix on the surface, and the water is delivered in pulses. The present invention also provides an apparatus adapted to carry out this process.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Tony Vessa
  • Video decoding with error detection and concealment
    Patent number: 8743970
    Abstract: A system and method of decoding input video information is disclosed which includes performing error detection for each video block of a frame, determining whether a scene change occurs for the frame, and when an error is detected in a video block, performing spatial concealment by concealing error of the erroneous video block using neighboring video information within the frame when the erroneous video block is intraframe encoded or when a scene change is detected for the frame, or performing temporal concealment by replacing the erroneous video block with a reference video block from a reference frame when the erroneous video block is interframe encoded and when a scene change is not detected for the frame. The method may further include detecting false frames based on comparing current and new frame number and picture order count values of a new slice.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhongli He, Xianzhong Li
  • Methods relating to intermetallic testing of bond integrity between bond pads and copper-containing bond wires
    Patent number: 8741666
    Abstract: Methods relating to intermetallic compound testing of copper-based wire bonds are provided. For example, a method is generally provided for testing the integrity of wire bonds formed between copper-containing wires and the bond pads of a plurality of microelectronic devices. In one embodiment, the method includes selecting at least one wire bond sample produced in conjunction with the wire bonds formed between the copper-containing wires and the bond pads of the microelectronic devices. One or more copper-containing wires of the wire bond sample are contacted with a liquid copper etchant, which contains a sulfate-based oxidizing agent dissolved in a solvent, to cause separation of the copper-containing wires from the bond pads and exposure of the underlying wire-pad interfaces. Intermetallic compounds formed at the exposed wire-pad interfaces are then measured to assess the integrity of the wire bonds.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weng F Yap, Lai Cheng Law, Boh Kid Wong
  • Timing control in synchronous memory data transfer
    Patent number: 8743613
    Abstract: A solid-state memory device has a memory interface that includes a timing signal port for receiving a timing signal, a data transfer port, a data transfer module for transferring blocks of data signals between the data transfer port and the memory module, and a selectable delay module for providing a selected delay between transitions in the data signals DQ and transitions in the timing signals DQS. The memory interface also has a delay controller for setting the selected delay, for detecting a variation in a delay produced by the selectable delay module relative to a reference delay, for controlling a pause in transfer of a block of the data signals DQ, and for adjusting the selected delay during the pause.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kailai Wang, Liang Zhao
  • METHODS FOR THE FABRICATION OF SEMICONDUCTOR DEVICES INCLUDING SUB-ISOLATION BURIED LAYERS
    Publication number: 20140147985
    Abstract: Methods for fabricating a semiconductor device are provided. In one embodiment, the method includes forming a Sub-Isolation Buried Layer (SIBL) stack over a semiconductor substrate. The SIBL stack includes a polish stop layer and a sacrificial implant block layer. The SIBL stack is patterned to create an opening therein, and the semiconductor substrate is etched through the opening to produce a trench in the semiconductor substrate. Ions are implanted into the semiconductor substrate at a predetermined energy level at which ion penetration through the patterned SIBL stack is substantially prevented to create a SIBL region beneath the trench. After ion implantation, a trench fill material is deposited over the SIBL stack and into the trench. The semiconductor device is polished to remove a portion of the trench fill material along with the sacrificial implant block layer and expose the polish stop layer.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jay P John, Scott A Hildreth, James A Kirchgessner
  • ENCAPSULANT FOR A SEMICONDUCTOR DEVICE
    Publication number: 20140145339
    Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sheila F. CHOPIN, Varughese MATHEW, Leo M. HIGGINS, III, Chu-Chung LEE
  • VOLTAGE RAMP-UP PROTECTION
    Publication number: 20140145765
    Abstract: Systems and methods for voltage ramp-up protection. In an illustrative, non-limiting embodiment, a method may include monitoring at least one of a first node or a second node, the first node configured to receive a first voltage greater than a second voltage present at a second node, and, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition. For example, the sneak condition may favor an excess current to flow from the first node to the second node. In some cases, counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value.
    Type: Application
    Filed: November 27, 2012
    Publication date: May 29, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jon S. Choy, Richard Titov Lara Saez, Luis Eduardo Rueda Guerrero
  • Lead-frame circuit package
    Patent number: 8736034
    Abstract: A lead-frame circuit package comprises a die and a substrate located thereon to route radio frequency signals to/from the die. The package preferably comprises an exposed pad on the die to receive a power amplifier device wherein the substrate is used to provide high-Q elements such as RF chokes on signal paths to/from the power amplifier device. In this manner, the design benefits from the power capabilities and improved grounding of a lead-frame conductor, whilst also achieving the routeing capabilities and small scale advantages provided by a multi-layer printed circuit substrate.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: May 27, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gilles Montoriol, Jr., Thierry Delaunay, Frederic Tilhac