Patents Assigned to Freescale
  • Level shifter circuit
    Patent number: 8723582
    Abstract: A single supply level shifter circuit for shifting the voltage level of an input voltage includes a voltage translation stage and a driver stage. The voltage translation stage receives the input voltage and a voltage supply and generates a first voltage. When a magnitude of the input voltage is LOW, the first voltage is LOW. The first voltage is provided to the driver stage, which inverts the first voltage to generate an output voltage that is at a voltage supply (Vdd) level, thereby level shifting the input voltage.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gaurav Goyal, Gaurav Gupta, Bipin B. Malhan
  • Object detection device with variable sensitivity electric field measurement circuit
    Patent number: 8720279
    Abstract: Three or more electrodes are arranged on either a window frame or window glass of an automobile. An electric field measurement unit measures the capacitance between various combinations of the electrodes to detect whether an object is located between the window frame and window glass. A control circuit varies the sensitivity of the electric field measurement unit by switching amongst the electrodes used for capacitance measurement based on the movement and position of the window glass.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Shunichi Ogawa
  • DELAY COMPENSATED CONTINUOUS TIME SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER
    Publication number: 20140125504
    Abstract: A continuous time sigma delta analog to digital converter is provided. The continuous time sigma delta analog to digital converter may include, but is not limited to, an analog to digital converter having a feedback loop, and a feedback loop controller coupled to the analog to digital converter, the feedback loop controller configured to adjust delay in the feedback loop by controlling a variable delay component in the feedback loop.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: Freescale Seconductor, Inc.
    Inventors: Brandt Braswell, Luis J . Briones
  • HARDWARE-BASED MEMORY INITIALIZATION
    Publication number: 20140129883
    Abstract: Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Henning F. Spruth, Qadeer A. Qureshi, Reinaldo Silveira
  • Protection Device And Related Fabrication Methods
    Publication number: 20140126091
    Abstract: Protection device structures and related fabrication methods are provided. An exemplary protection device includes a first bipolar junction transistor, a second bipolar junction transistor, a first zener diode, and a second zener diode. The collectors of the first bipolar junction transistors are electrically coupled. A cathode of the first zener diode is coupled to the collector of the first bipolar transistor and an anode of the first zener diode is coupled to the base of the first bipolar transistor. A cathode of the second zener diode is coupled to the collector of the second bipolar transistor and an anode of the second zener diode is coupled to the base of the second bipolar transistor. In exemplary embodiments, the base and emitter of the first bipolar transistor are coupled at a first interface and the base and emitter of the second bipolar transistor are coupled at a second interface.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chai Ean Gill, Changsoo Hong, Rouying Zhan, William G. Cowden
  • SENSOR PACKAGING METHOD AND SENSOR PACKAGES
    Publication number: 20140124958
    Abstract: A method (80) entails providing (82) a structure (117), providing (100) a controller element (102, 24), and bonding (116) the controller element to an outer surface (52, 64) of the structure. The structure includes a sensor wafer (92) and a cap wafer (94) Inner surfaces (34, 36) of the wafers (92, 94) are coupled together, with sensors (30) interposed between the wafers. One wafer (94, 92) includes a substrate portion (40, 76) with bond pads (42) formed on its inner surface (34, 36). The other wafer (94, 92) conceals the substrate portion (40, 76). After bonding, methodology (80) entails forming (120) conductive elements (60) on the element (102, 24), removing (126) material sections (96, 98, 107) from the wafers to expose the bond pads, forming (130) electrical interconnects (56), applying (134) packaging material (64), and singulating (138) to produce sensor packages (20, 70).
    Type: Application
    Filed: January 9, 2014
    Publication date: May 8, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Philip H. Bowles, Paige M. Holm, Stephen R. Hooper, Raymond M. Roop
  • SAFETY CRITICAL APPARATUS AND METHOD FOR CONTROLLING DISTRACTION OF AN OPERATOR OF A SAFETY CRITICAL APPARATUS
    Publication number: 20140129001
    Abstract: A safety critical apparatus comprises a set of safety relevant modules; one or more comfort modules having one or more user interfaces; and a distraction controlling device arranged to adapt at least one of the one or more user interfaces to a current situation of operation of the safety critical apparatus.
    Type: Application
    Filed: July 20, 2011
    Publication date: May 8, 2014
    Applicant: Freescale Semicondudctor, Inc.
    Inventors: Michael Staudenmaier, Davor Bogavac
  • AMPLIFIER CALIBRATION
    Publication number: 20140125409
    Abstract: A system and method of calibrating an amplifier are presented. The amplifier has a first amplification path and a second amplification path. A first state of the amplifier is identified defining a first phase shift of the first path and a second phase shift of the second path resulting in a maximum efficiency of the amplifier when an attenuation of the first path and an attenuation of the second path are set to first attenuation values. The attenuation of the first path and the attenuation of the second path is set to achieve a maximum efficiency of the amplifier when the phase shift of the first path and the phase shift of the second path are set according to the first state.
    Type: Application
    Filed: January 10, 2014
    Publication date: May 8, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Abdulrhman M.S. Ahmed, Paul R. Hart, Ramanujam Shinidhi Embar
  • Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage
    Patent number: 8716089
    Abstract: A thermal oxide is formed in an NVM region and a logic region. A polysilicon layer is formed over the thermal oxide and patterned to form a dummy gate and a select gate in the logic and NVM regions, respectively. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, forming an opening. A second dielectric layer is formed over the select gate and within the opening, and a gate layer is formed over the second dielectric layer and within the opening, wherein the gate layer within the opening forms a logic gate and the gate layer is patterned to form a control gate in the NVM region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Frank K. Baker, Jr., Mehul D. Shroff
  • Circuit and method for speed monitoring of an electric motor
    Patent number: 8716971
    Abstract: A circuit for speed monitoring of an electric motor comprises a circuit for generating a time-frame signal, a circuit for receiving a first signal from a chopper driver circuit designed to drive the electric motor, a circuit for detecting chopper pulses in the first signal, a pulse counter, and a circuit for at least one of outputting and evaluating a state of the pulse counter, after the inactive state of the time-frame has been indicated. The time-frame signal indicates when a time-frame of predefined length changes from an inactive state to an active state and indicates when the time-frame changes back from the active state to the inactive state. The pulse counter is designed to count the detected chopper pulses while the active state is indicated by the circuit for generating the time-frame signal.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Daniel Lopez-Diaz, Hans Gommeringer
  • Pressure sensor and method of packaging same
    Patent number: 8716846
    Abstract: A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinzhong Yao, Wai Yew Lo, Lan Chu Tan, Xuesong Xu
  • Non-volatile memory (NVM) reset sequence with built-in read check
    Patent number: 8719646
    Abstract: A new, robust non-volatile memory (NVM) reset sequence is provided in accordance with at least one embodiment, which, after reading a Test NVM portion and overwriting NVM configuration registers' default values with the values read from the Test NVM portion, does a read integrity check. If the read integrity check passes, a reset process will conclude. Otherwise, if the read integrity check fails, the reset process will re-try reading the Test NVM and overwriting the NVM configuration registers' default values. If the read integrity check still fails after a maximum number of re-tries, a fail flag will be set, and the predetermined “safe” default values will be reloaded to the NVM configuration registers, thereby assuring that the NVM device is operational.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chen He, Kelly K. Taylor
  • System and method for soft error detection in memory devices
    Patent number: 8717829
    Abstract: A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ashish Sharma, James B. Eifert, Amit Kumar Gupta, Thomas W. Liston, Jehoda Refaeli
  • Method for plating a semiconductor package lead
    Patent number: 8716066
    Abstract: A method of forming a packaged semiconductor device includes loading an array of package sites in position for saw singulation, saw singulating the array of package sites, and performing a non-electrolytic plating operation on exposed lead tips of individual packages from the array of package sites as the array of package sites is saw singulated.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Leo M. Higgins, III
  • Logic transistor and non-volatile memory cell integration
    Patent number: 8716781
    Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 6, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • SEMICONDUCTOR DEVICE WITH THERMAL DISSIPATION LEAD FRAME
    Publication number: 20140117521
    Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chetan Verma, Piyush Kumar Mishra, Cheong Chiang Ng
  • GATE DRIVER WITH DESATURATION DETECTION AND ACTIVE CLAMPING
    Publication number: 20140118874
    Abstract: Apparatus, systems, and methods are provided for protecting a switching device using a gate driver device. An exemplary gate driver system includes an interface for coupling to a switching device, a desaturation detection arrangement coupled to the interface to detect a desaturation condition based on an electrical characteristic at the interface, and a deactivation arrangement coupled to the interface to deactivate the switching device in a manner that is influenced by the electrical characteristic at the interface. In one embodiment, the switching device is deactivated by providing a deactivation current to a control terminal of the switching device and adjusting the deactivation current based on an electrical characteristic at the interface.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Ibrahim S. Kandah
  • RELAXATION OSCILLATOR
    Publication number: 20140118078
    Abstract: A relaxation oscillator for generating an output clock signal includes a RC circuit, a bias generation stage, first and second comparator stages, and a logic circuit. The RC circuit generates first and second comparator input signals that are transmitted to the first and second comparator stages. The bias generation stage generates first and second bias voltages that are provided to each of the first and second comparator stages. The first and second comparator stages generate first and second comparator output signals, respectively, based on the first and second comparator input signals and the first and second bias voltages. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: FREESCALE-SEMICONDUCTOR, INC.
    Inventors: Anand Kumar Sinha, Sanjay K. Wadhwa
  • METHOD AND APPARATUS FOR A TUNABLE DRIVER CIRCUIT
    Publication number: 20140117953
    Abstract: A driver circuit having an adjustable output signal includes a logic circuit configured to receive an input signal into a first input terminal and an output circuit coupled to the logic circuit, wherein the output circuit is configured to generate, at an output terminal of the output circuit, an output signal having a signal level that changes in response to a signal level of the input signal. The driver circuit further includes a feedback circuit coupled to a second input terminal of the logic circuit. The feedback circuit includes first and second gate terminals coupled to the output terminal and a third gate terminal coupled to a control signal supply, wherein the feedback circuit is configured to control a maximum level of the output signal from the driver circuit based on an operating threshold of the feedback circuit as set by a control signal generated by the control signal supply.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: ALEXANDER B. HOEFLER, HECTOR SANCHEZ
  • SYSTEM AND METHOD FOR ASSIGNING A MESSAGE
    Publication number: 20140122735
    Abstract: A processor of a plurality of processors includes a processor core and a message manager. The message manager is in communication with the processor core. The message manager to receive a message from a second processor of the plurality of processors, to identify a classification rule for the message based on bits in a header of the message, and to create a queue identifier for the message using bits of a payload of the message, wherein the queue identifier is associated with a queue of the processor core.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tommi N. Jokinen, David B. Kramer, Kun Xu