Abstract: A micro or nano electromechanical transducer device formed on a semiconductor substrate comprises a movable structure which is arranged to be movable in response to actuation of an actuating structure. The movable structure comprises a mechanical structure having at least one mechanical layer having a first thermal response characteristic, at least one layer of the actuating structure having a second thermal response characteristic different to the first thermal response characteristic, and a thermal compensation structure having at least one thermal compensation layer. The thermal compensation layer is different to the at least one layer and is arranged to compensate a thermal effect produced by the mechanical layer and the at least one layer of the actuating structure such that the movement of the movable structure is substantially independent of variations in temperature.

Abstract: A method of encoding a video frame is disclosed in which video slices of the video frame are initially encoded in parallel using both interframe encoding and intraframe encoding. Then, after a first predetermined minimum amount of the video frame has been encoded, the method includes periodically determining whether the amount of intraframe encoded information for the frame achieves a first threshold, and when the first threshold is achieved, encoding the remainder of the video frame using only intraframe encoding. The method may include determining whether a lower second threshold is achieved based on relative complexity of the frame and quantization. The method may include performing similar comparisons on a slice by slice basis in which any one or more of the processing devices skips motion estimation and interframe encoding for corresponding video slices. A video encoder is disclosed which includes multiple processing devices and a shared memory.

Abstract: A memory device includes a word line driver circuit, a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit, and a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit. The write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit.

Abstract: A method and circuit for providing on-chip measurement of the delay between two signals includes first and second delay chains (241, 242) having different delay values connected to sampling latches (222-227) which each include a data input coupled between adjacent delay elements of the first delay chain and a clock input coupled between adjacent delay elements of the second delay chain, thereby capturing a high precision delay measurement for the signals.

Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the first and second adjustable phase shifters and attenuation levels to be applied by the first and second adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the first and second adjustable phase shifters and the first and second adjustable attenuators.

Abstract: A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.

Abstract: Schmitt trigger with rail-to-rail or near rail-to-rail hysteresis. In some embodiments, a method includes switching an output of a Schmitt trigger from a first logic state to a second state in response to an input meeting a threshold, where the threshold is applied to a first transistor of a first doping type and the input is applied to a second transistor of the first doping type, the first and second transistors operably coupled to each other through a current mirror of a second doping type. The first doping type may be an n-type, the second doping type may be a p-type, and the threshold may be a rising threshold having a value within 10% of a supply voltage. Alternatively, the first doping type may be a p-type, the second doping type may be an n-type, and the threshold may be a falling threshold having a value within 10% of ground.

Abstract: A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.

Abstract: A non-overlapping clock generator circuit supplies clock signals to a stage of a pipelined ADC, which includes parallel switched capacitor circuitry. The non-overlapping clock generator circuit includes: a first trigger generation circuit that generates first and second trigger signals; a second trigger generation circuit that generates third and fourth trigger signals; a first clock generation branch that receives the first, second and fourth trigger signals and generates first sampling cycle and delayed sampling cycle clock signals; a second clock generation branch that receives the first, second and third trigger signals and generates second sampling cycle and delayed sampling cycle clock signals; a third clock generation branch that receives the second trigger signal and generates first gain cycle and delayed gain cycle clock signals; and a fourth clock generation branch that receives the first trigger signal and generates second gain cycle and delayed gain cycle clock signals.

Abstract: A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.

Abstract: An integrated circuit, comprises a power supply node being connectable to a voltage supply (Vdd); a ground node connectable to ground (GND); and an electrostatic discharge protection structure for diverting an electrostatic discharge away from protected parts of the integrated circuit. A gated domain is present which is supply gated and/or ground gated with respect to the power supply node and/or the ground node, as well as a gating switch for gating the gated domain relative to the power supply node and/or the ground node. The gating switch enables in a connecting state, and in a disconnecting state inhibits, an electrical connection between the gated domain and at least one of: the power supply node and the ground node. The integrated circuit includes ESD gating control circuitry for controlling in case of an electrostatic discharge event the gated domain to be electrically connected to the power supply node and/or the ground node.

Abstract: Embodiments of a semiconductor device include a semiconductor substrate having a first surface and a second surface opposed to the first surface, a trench formed in the semiconductor substrate and extending from the first surface partially through the semiconductor substrate, a gate electrode material deposited in the trench, and a void cavity in the semiconductor substrate between the gate electrode material and the second surface. A portion of the semiconductor substrate is located between the void cavity and the second surface.

Abstract: A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element.

Abstract: A System on a Chip (SoC) has a first set of switches, each having first terminals for routing SoC signals and a second terminal, and a second set of switches. Each switch of the second set of switches has third terminals for routing signals with the first set of switches, and a fourth terminal. A SoC control module defines a switching configuration, and includes a first memory portion for storing a first switching protocol for the first set of switches. This defines, for a switch of the first set of switches, an electrical path between one of the first terminals and the second terminal. A second memory portion stores a second switching protocol for the second set of switches, and defines, for a switch of the second set of switches, an electrical path between one of the third terminals and the fourth terminal.

Abstract: A compiler and method for compiling source code comprising: a library of code patterns and control flow information for each code pattern, wherein each code pattern comprises one or more variable; and a processor arranged to: evaluate the control flow of an expression in the source code, wherein the expression comprises one or more variable, match the expression to one of the code patterns in the library based on the evaluated control flow information, assign value numbers to the one or more variable within the expression, determine if the expression and the matched code pattern are equivalent based on the assigned value numbers, and replace the expression in the source code with a replacement expression if the expression and the matched code pattern are equivalent.

Abstract: Threads may be scheduled to be executed by one or more cores depending upon whether it is more desirable to minimize power or to maximize performance. If minimum power is desired, threads may be schedule so that the active devices are most shared; this will minimize the number of active devices at the expense of performance. On the other hand, if maximum performance is desired, threads may be scheduled so that active devices are least shared. As a result, threads will have more active devices to themselves, resulting in greater performance at the expense of additional power consumption. Thread affinity with a core may also be taken into consideration when scheduling threads in order to improve the power consumption and/or performance of an apparatus.

Abstract: Systems and methods for low-power voltage tamper detection are described. In some embodiments, an integrated circuit may include source-follower circuitry configured to produce a scaled down supply voltage. The integrated circuit may also include undervoltage detection circuitry coupled to the source-follower circuitry, the undervoltage detection circuitry configured to output a first signal having a first logic value if the scaled down supply voltage is greater than a low threshold voltage or a second logic value if the scaled down supply voltage is smaller than the low threshold voltage. Additionally or alternatively, the integrated circuit may include overvoltage detection circuitry coupled to the source-follower circuitry, the overvoltage detection circuitry configured to output a second signal having the first logic value if the scaled down supply voltage is smaller than a high threshold voltage or the second logic value if the scaled down supply voltage is greater than the high threshold voltage.

Abstract: An electrostatic discharge (ESD) protection circuit includes a clamping transistor and a trigger circuit. The clamping transistor is coupled between a first power supply voltage terminal and a second power supply voltage terminal. The trigger circuit includes a detection circuit, first and second transistors, and first, second, and third inverters. The detection circuit is coupled to monitor a power supply voltage. The first inverter has an input terminal coupled to a current electrode of the first transistor, and an output terminal coupled to a control electrode of the clamping transistor. The second inverter and the third inverter form a feedback path from the output of the first inverter to the control electrode of the first transistor. The second inverter has a switching voltage that is lower than a midpoint voltage of a power supply voltage provided to the first and second power supply voltage terminals.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: Systems and methods for voltage ramp-up protection. In an illustrative, non-limiting embodiment, a method may include monitoring at least one of a first node or a second node, the first node configured to receive a first voltage greater than a second voltage present at a second node, and, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition. For example, the sneak condition may favor an excess current to flow from the first node to the second node. In some cases, counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value.