Abstract: A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.

Abstract: An integrated circuit device comprising at least one instruction processing module, at least one memory comprising at least one memory bank configurable to operate in a first functional mode and at least one further, lower-power mode, and at least one memory mode control module arranged to control switching of the at least one memory bank between the first functional mode and the at least one further, lower-power modes.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

Abstract: A conference call system comprises an input interface for receiving during a conference call at least two input streams of audio signal, each from another source. A selection unit is connected to the input interface, for selecting a number of dominant speaker streams out of the input streams, the number being less than or equal to a maximum number of dominant speakers value and each of the dominant speaker streams representing speech from a respective dominant speaker. A mixer is connected to the selection unit, for mixing the selected streams into an output stream. The conference call system comprises an output interface for outputting the output stream and a selection control unit connected to the selection unit and the input interface, for dynamically setting, during the conference call, the maximum number of dominant speakers value based on dynamics of the conference call.

Abstract: A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized.

Abstract: An integrated circuit comprises a shared resource for providing data to a buffer. The buffer is coupled to a buffer level monitor and a filling circuit. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition involving the monitored level of data in the buffer indicates an anticipated violation of a timing constraint.

Abstract: An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled.

Abstract: In a data processing system, a method includes a first master initiating a transaction via a system interconnect to a target device. After initiating the transaction, a snoop request corresponding to the transaction is provided to a cache of a second master. The transaction is completed. After completing the transaction, a snoop lookup operation corresponding to the snoop request in the cache of the second master is performed. The transaction may be completed prior to or after providing the snoop request. In response to performing the snoop lookup operation, a snoop response may be provided, where the snoop response is provided after completing the transaction. When the snoop response indicates an error, a snoop error may be provided to the first master.

Abstract: A package structure includes a package substrate having a top surface and a bottom surface. A semiconductor die having a top surface and a bottom surface. The semiconductor die is mounted to the package substrate. The bottom surface of the semiconductor die is adjacent to the top surface of the package substrate. An air gap is between the bottom surface of the package substrate and the bottom surface of semiconductor die.

Abstract: A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.

Abstract: A method of allocating a plurality of communication channels of a network, for a plurality of network stations of the network. The method comprises generating a common transmission message for the plurality of network stations and transmitting the generated transmission message to the plurality of network stations. The message comprises channel allocation information allowing an allocation of channels by the network stations, the information relating to each of the plurality of network stations. A network managing station for communicating with the plurality of network stations, there being a plurality of communication channels available for use by the plurality of network stations. The network managing station comprises a processor, arranged to generate the common transmission message for the plurality of network stations and a transmitter arranged to transmit the generated transmission to said plurality of networks.

Abstract: A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.

Abstract: A configurable multistage charge pump including multiple pumpcells, at least one bypass switch and control logic. The pumpcells are coupled together in series including a first pumpcell receiving an input voltage and at least one remaining pumpcell including a last pumpcell which generates an output voltage. Each bypass switch is coupled to selectively provide the input voltage to a pumpcell input of a corresponding one of the remaining pumpcells. The control logic is configured to determine one of multiple voltage ranges of the input voltage, to enable each pumpcell for a first voltage range and to disable and bypass at least one pumpcell for at least one other voltage range. A method of operating a multistage charge pump including detecting an input voltage, selecting a voltage range based on an input voltage, and enabling a number of cascaded pumpcells corresponding to the selected voltage range.

Abstract: Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages.

Abstract: A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices.

Abstract: A printed circuit board including a first outer layer, a second outer layer and an integrated circuit mounted on the second outer layer. The integrated circuit has a single exposed pad electrically connected to a ground reference, a first supply pin electrically connected to a first power supply and a second supply pin electrically connected to a second power supply, wherein the first power supply is configured to generate a first supply current with frequency components higher than the frequency components of a second supply current generated by the second power supply.

Abstract: An LDMOS transistor includes a substrate of semiconductor material, an insulator layer overlying the substrate, a semiconductor layer overlying the insulator layer, a RESURF region, and a gate. The semiconductor layer includes a first conductivity type well region, a second conductivity type source region in contact with the first conductivity type well region, a second conductivity type drain region. The RESURF region includes at least one first conductivity type material portion, and at least one portion of the at least one first conductivity type material portion electrically coupled to the first conductivity type well region. A semiconductor material having a second conductivity type is located below the RESURF region. The second conductivity type semiconductor material is also located over a part of the RESURF region. The gate is located over the first conductivity type well region and over the RESURF region.

Abstract: A method and apparatus automatically maintains a JESD204 serial data link (252) as active by using an idle signal (254) and multiplexer selection circuit (247) to selectively switch signal data samples (246) and dummy samples (0, . . . 0) onto a serial interface input to a JESD module (248) for serialization into a plurality of symbols for transmission over the JESD204 serial data link (252) in response to a transmit clock signal (253) so that serialized symbols generated from signal data samples are transmitted when there are signal data samples available, and serialized symbols generated from dummy samples are transmitted when there are no signal data samples available.

Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a cellular network. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in multiple cellular networks.

Abstract: A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.