Abstract: A data processing system has a cache which receives both non-debug snoop requests and debug snoop requests for processing. The non-debug snoop requests are generated in response to transactions snooped from a system interconnect. Debug control circuitry that is coupled to the cache provides the debug snoop requests to the cache for processing. The debug snoop requests are generated in response to debug snoop commands from a debugger and without the use of the system interconnect. In one form snoop circuitry has a snoop request queue having a plurality of entries, each entry for storing a snoop request. A debug indicator corresponding to each snoop request indicates whether the snoop request is a debug snoop request or a non-debug snoop request.

Abstract: A method of and apparatus for fault detection utilizing a diagnostic procedure by a diagnostic device to detect a short circuit between at least two of a plurality of load electrical connections, the diagnostic procedure comprising applying a test electrical signal to each of the load electrical connections in turn and whilst applying the test electrical signal to a first one of the load electrical connections, detecting whether an electrical output is present, in response, on any other of the load electrical connections, wherein the detecting by the diagnostic device includes applying the test electrical signal to the first one of the load electrical connections in an operational mode of the apparatus when an electrically controlled switch connected to the first one of the load electrical connections is in an off state.

Abstract: A method for encoding an image. The method comprises: dividing the image into a plurality of variable sized blocks, encoding each sub-block using variable bit rate encoding, storing the encoded sub-blocks, generating a marker matrix, and storing the marker matrix for use in decoding the image.

Abstract: A thermal sensor system which includes a thermal sensor and a voltage control network which applies a reference voltage level and a delta voltage level to the same or different thermal sensors. The thermal sensor develops a reference current signal in response to the reference voltage level and a delta current signal in response to the delta voltage level. A current gain network adjusts gain of the delta current signal. A current compare sensor, which is responsive to the reference current signal and the delta current signal, provides a comparison metric. A controller controls the current gain network to adjust gain of the delta current signal while monitoring the comparison metric to determine a gain differential value indicative of a current ratio between the current signals. The controller determines a temperature value based on the gain differential value. A LUT may be used to retrieve the temperature.

Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect.

Abstract: An integrated circuit device comprising at least one electrostatic discharge (ESD) clamp device. The at least one ESD clamp device comprises a first channel input, a second channel input, and a control input arranged to receive a control signal. The at least one ESD clamp device is arranged to selectively operate in a conductive state in which the at least one ESD clamp device permits current to flow between the first and second channel inputs thereof based at least partly on the received control signal. The integrated circuit device further comprises at least one biasing module. The at least one biasing module comprises at least one output operably coupled to the control input of the at least one ESD clamp device and at least one input arranged to receive a thermal regulation signal. The at least one biasing module being arranged to apply a bias to the control signal for the at least one ESD clamp device based at least partly on the received thermal regulation signal.

Abstract: A thermal sensor system including at least one thermal sensor, a voltage control network, a current gain network, a current compare sensor, and a controller. The voltage control network applies reference and delta voltage levels to a thermal sensor, which develops reference and delta current signals. The current gain network is used to adjust current gain. The current compare sensor is responsive to the reference and delta current signals and provides a comparison metric. The controller selects a temperature subrange and controls the current gain network to adjust the gain of the delta current signal to determine a gain differential value indicative of the temperature. The controller may select from among different sized thermal sensors, current mode gain values, and control voltages corresponding with each of multiple temperature subranges. Any one or more of these parameters may be adjusted to adjust an operating point for selecting a corresponding temperature subrange.

Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.

Abstract: A method is for operating a memory having a group of non-volatile memory cells. A first programming pulse is applied to a subset of the group of non-volatile memory cells. The subset needs additional programming. A portion of the subset still needing additional programming is identified. A ratio of the number of memory cells in the subset and the number of memory cells in the portion is determined. A size of a second programming pulse based on the ratio is selected. The second programming pulse is applied to the portion.

Abstract: A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.

Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.

Abstract: In a semiconductor device having multiple tiers of bond wires extending in a first direction, dummy insulated bond wires extend in a second direction orthogonal to the first direction and between the wire tiers to support the wires in an upper tier to prevent them from sagging and contacting wires in a lower tier.

Abstract: An integrated protection circuit for protecting a main circuit from spurious high amplitude voltage signals is provided, wherein the main circuit has a main circuit input terminal connected to an input line, and the protection circuit comprises a transistor, a resistor and a capacitor. The transistor has a first electrode connected to the input line, a second electrode connected to a common reference, and a control electrode connected to the resistor. The resistor is connected to the common reference; and the capacitor is implemented as a fringe capacitor between the input line and the control electrode or a conductive line connected to the control electrode.

Abstract: An embodiment of an equalizer includes a voltage-to-current converter and a current-to-voltage converter. The voltage-to-current converter is configured to convert a differential input voltage to a differential current, and includes a differential amplifier with a first transistor and a second transistor, and a first source degeneration circuit coupled between the first transistor and the second transistor. An embodiment of the first source degeneration circuit includes a first resonant circuit. The current-to-voltage converter is coupled to the voltage-to-current converter, and is configured to convert the differential current to a differential output voltage. The current-to-voltage converter includes a first inverter with a first feedback circuit and a second inverter coupled to the first inverter, which includes a second feedback circuit. An embodiment of the first feedback circuit includes a second resonant circuit, and an embodiment of the second feedback circuit includes a third resonant circuit.

Abstract: A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate.

Abstract: An integrated circuit device comprises a first clock signal source, arranged to provide at least one first clock signal; a second clock signal source, arranged to provide at least one second clock signal different from the at least one first clock signal; and a plurality of sequential logic cells, at least one of the plurality connected to receive, in a first mode, the at least one first clock signal or at least one clock signal derived from the at least one first clock signal, and to receive, in a second mode, the at least one second clock signal or at least one clock signal derived from the at least one second clock signal; wherein in the second mode the at least one second clock signal is adapted to the at least one of the plurality of sequential logic cells to generate in at least a portion of the integrated circuit device a current consumption when the at least one first clock signal is not a toggling signal.

Abstract: Apparatus arranged to perform data multiplexing or demultiplexing or a non-transitory computer readable medium comprising a computer program which, when executed by a computer, carries out a method of multiplexing or demultiplexing data, the apparatus comprising a memory, an interface, and a processing unit arranged to determine locations of corresponding regions of the memory for corresponding channels based on data sizes and time-unit-numbers that have passed since a previous corresponding quantity of channel data for a corresponding channel was last stored in the memory or processed, wherein the data sizes and time-unit numbers correspond to one or more channels of the plurality of channels, such that the processing unit will not store the corresponding quantity of the channel data, for each corresponding channel of the plurality of channels, at a location in the memory that is currently storing any channel data that has not yet been output or processed.

Abstract: An adjustable power splitter includes: a power divider with an input and a plurality, N, of divider outputs; a plurality, N, of adjustable phase shifters and a plurality, N, of adjustable attenuators series coupled to the divider outputs and providing a plurality, N, of power outputs; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the adjustable phase shifters and attenuation levels to be applied by the adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the adjustable phase shifters and the adjustable attenuators.

Abstract: A voltage regulating circuit is provided for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level. The voltage regulating circuit comprises a voltage regulator and a reference level generator. The reference level generator generates an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment. The voltage regulator regulates said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level. A method of regulating an output voltage is also disclosed.