Abstract: A method of manufacturing a semiconductor device on a substrate. The method may include forming a non-volatile memory in a memory area of the substrate. The forming non-volatile memory on a substrate may include formation in the memory area of a floating gate structure and of a control gate structure which is in a stacked configuration with the floating gate structure. One or more gate material layer may be formed in a logic area of the substrate. After forming the control gate structure and the gate material layer, a filling material layer may be deposited over the logic area and the memory area. The filling material layer may be partially removed by reducing the thickness of the filling material in the logic area and the memory area, at least until a top surface of the one or more gate material layer is exposed. Logic devices may be formed in the logic area, the formation may include forming a logic gate structure from the gate material layer.

Abstract: A multi-threaded processor that is capable of responding to, and processing, multiple low-latency-tolerant events concurrently and while using relatively slow, low-power memories is disclosed. The illustrative embodiment comprises a multi-threaded processor, which itself comprises a context controller and a plurality of hardware contexts. Each hardware context is capable of storing the current state of one thread in a form that enables the processor to quickly switch to or from the execution of that thread. To enable the processor to be capable of responding to low-latency-tolerant events quickly, each thread—and, therefore, each hardware context is prioritized—depending on the latency tolerance of the thread responding to the event.

Abstract: A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

Abstract: A system comprises signal processing logic that is operably coupled to at least one memory element and is arranged to enable access to the at least one memory element. The signal processing logic is arranged to receive a security key, generate a system key using the received security key and a system specific seed, perform a comparison of the generated system key to a reference key stored in an area of memory of the at least one memory element. The signal processing logic is also arranged to configure a level of access to the at least one memory element based at least partly on the comparison of the generated system key to the reference key stored in memory.

Abstract: A storage element within a circuit design is identified. The storage element is replaced with both a first storage cell and a second storage cell. The second storage cell operates as a redundant storage cell to the first storage cell. An output of the first storage cell is connected to a first input of a comparator and an output of the second storage cell is connected to a second input of the comparator. The comparator provides an error indicator. Placement of the first storage cell, the second storage cell, the comparator, and one or more intervening cells is determined. The one or more intervening cells are placed between the first storage cell and the second storage cell. An integrated circuit is created using the comparator, the first storage cell, the second storage cell, the one or more intervening cells, and the determined placement.

Abstract: A semiconductor fabrication process includes masking a first region, e.g., an NMOS region, of a semiconductor wafer, e.g., a biaxial, tensile strained silicon on insulator (SOI) wafer and creating recesses in source/drain regions of a second wafer region, e.g., a PMOS region. The wafer is then annealed in an ambient that promotes migration of silicon. The source/drain recesses are filled with source/drain structures, e.g., by epitaxial growth. The anneal ambient may include a hydrogen bearing species, e.g., H2 or GeH2, maintained at a temperature in the range of approximately 800 to 1000° C. The second region may be silicon and the source/drain structures may be silicon germanium. Creating the recesses may include creating shallow recesses with a first etch process, performing an amorphizing implant to create an amorphous layer, performing an inert ambient anneal to recrystallize the amorphous layer, and deepening the shallow recesses with a second etch process.

Abstract: In a making a semiconductor device, a patterning stack above a conductive material that is to be etched has a patterned photoresist layer that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer. The TEOS layer is deposited at a lower temperature than is conventional. The low temperature TEOS layer is over an organic anti-reflective coating (ARC) that is over the conductive layer. The low temperature TEOS layer provides adhesion between the organic ARC and the photoresist, has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC, to reduce undesired reflection.

Abstract: Sequential video data frames are encoded using cores including a first core and a second core. A first beginning frame is divided into slices. The first core is assigned to process a first slice. The second core is assigned to process a second slice. The first beginning frame is processed using the cores which results in a first ending frame in which the first slice was partitioned into a third slice and a fourth slice. The third slice was processed by the first core. The fourth slice and the second slice were processed by the second core. A second beginning frame, which immediately follows the first ending frame, is divided into a second plurality of slices. The first core is assigned to the third slice. The second core is assigned to a fifth slice which has a size equal to a sum of the second and fourth slices.

Abstract: A peak detection/digitization circuit includes a plurality of level detect units, each having a comparator and a flip-flop with a clock input responsive to the output of the comparator. For a detection period, each level detect unit configures a data output signal of the flip-flop to a first data state responsive to a start of the detection period. Further, each level detect unit is configured to enable the comparator responsive to the data output signal having the first data state or a second data state, respectively. While the comparator is enabled during the detection period, the level detect unit configures the data output signal of the flip-flop responsive to a comparison of an input signal to a corresponding reference voltage level by the comparator. The data output signals of the flip-flops of the level detect units at the end of the detection period are used to determine a digital value representative of a peak voltage level of the input signal.

Abstract: A method of forming a through silicon via includes forming a via opening in a substrate using a hard mask, wherein a polymer is formed in the via opening. A first wet clean removes a first portion of the polymer and forms a first carbon containing oxide along portions of the sidewalls. A first ash process modifies the first carbon containing oxide and removes a second portion of the polymer. A first wet etch removes the modified first carbon containing oxide and a third portion of the polymer. A second ash process forms a second carbon containing oxide along at least a portion of the sidewalls. A second wet etch process removes the second carbon containing oxide and a fourth portions of the polymer. A third ash process forms a third carbon containing oxide along portions of the sidewalls and removes any remaining portions of the polymer.

Abstract: A semiconductor device is formed. A first gate dielectric layer is formed over the semiconductor layer. A first conductive layer is formed over the first gate dielectric. A first separation layer is formed over the first conductive layer. A trench is formed in the semiconductor layer to separate the first mesa and the second mesa. The trench is filled with an isolation material to a height above a top surface of the first conductive layer. The first conductive layer is removed from the second mesa. A second conductive layer is formed over the first separation layer of the first mesa and over the second mesa. A planarizing etch removes the second conductive layer from over the first mesa. A first transistor of a first type is formed in the first mesa, and a second transistor of a second type is formed in the second mesa.

Abstract: Power supply switching apparatus comprising an output switch for supplying power from a power supply to a load connected to an output terminal, a driver for controlling turn-on of said output switch, and a control signal generator for controlling said driver to produce a desired progressive turn-on characteristic. The apparatus also includes overload detection means responsive to a parameter of the load relative to a reference signal to provide a fault signal in case of detection of an overload condition after a turn-on phase of said output switch. The control signal generator is responsive to the reference signal to activate said overload detection means to provide a fault signal during the turn-on phase of the output switch even in presence of a severe overload condition at the output terminal.

Abstract: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.

Abstract: Systems and methods are provided for determining the value of a capacitance. A system for sensing capacitance comprises an oscillator arrangement comprising a plurality of oscillators and a mismatch compensation arrangement coupled between the oscillator arrangement and a first capacitive element having a first capacitance. The mismatch compensation arrangement is configured to selectively couple the first capacitive element to a respective oscillator of the plurality of oscillators, wherein an oscillation frequency of the respective oscillator is influenced by the first capacitance.

Abstract: A capped micro-electro-mechanical systems (MEMS) device is formed using a device wafer and a cap wafer. The MEMS device is located on a frontside of the device wafer. A frontside of a cap wafer is attached to the frontside of the device wafer. A first stressor layer having a tensile stress is applied to a backside of the cap wafer after attaching the frontside of the cap wafer to the frontside of the device wafer. The first stressor layer and the cap wafer are patterned to form an opening through the first stressor layer and the cap wafer after applying the first stressor layer. A conductive layer is applied to the backside of the cap wafer, including through the opening to the frontside of the device wafer.

Abstract: For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.

Abstract: A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.

Abstract: A performance monitoring device and method are disclosed. The device monitors performance events of a processor. A counter is adjusted in response to the occurrence of a particular performance event. The counter can be associated with a particular instruction address range, or a data address range, so that the counter is adjusted only when the performance event occurs at the instruction address range or the data address range. Accordingly, the information stored in the counter can be analyzed to determine if a particular instruction address range or data address range results in a particular performance event. Multiple counters, each associated with a different performance event, instruction address range, or data address range, can be employed to allow for a detailed analysis of which portions of a program lead to particular performance events.

Abstract: A charge pump has circuitry and implements a method for monitoring a synchronous load by using a first voltage threshold below a target output voltage and a second voltage threshold above a target output voltage. An output terminal is coupled to the load. Charge is demanded by clocking the load. When the target output voltage passes below the first voltage threshold, a first value representing a present size of a charging capacitance is stored as a stored first value, and a second stored value representing a needed changed size of the charging capacitance is used. The present size of the charging capacitance is changed in response to the passing of the target output voltage below the first voltage threshold. When demand for charge from the load is reduced, a present value is saved and a prior value is restored to change the size of the charging capacitance.

Abstract: Determination of an estimated initial angular position of the rotor of an AC motor includes application of voltages corresponding to a high frequency reference signal vector to the stator windings of the motor and production of an estimated initial angular position of the rotor as a function of the resulting q-axis stator current component iq_HF, adjustment of transformation of signal vectors from stationary to rotating coordinates and vice versa using the estimated angular position, and production of an adjusted estimated angular position of the rotor as a function of the q-axis stator current component as adjusted.