Abstract: A buffer amplifier having a wide output voltage range includes a first source follower circuit having a first current source and a first transistor, and a second source follower circuit having a second current source and a second transistor. The first source follower circuit has an output terminal connected to a gate of a third transistor and a source of a fourth transistor. The second source follower circuit has an output terminal connected to a gate of a fifth transistor and a source of a sixth transistor. First and second voltages are respectively supplied to the gates of the fourth and sixth transistors. The sixth transistor is operated in place of the fifth transistor in a low voltage range, and the fourth transistor is operated in place of the third transistor in a high voltage range.

Abstract: A method is provided for creating a barrier layer (217) on a substrate comprising a dielectric layer (203) and a metal interconnect (211). In accordance with the method, the substrate is treated with a first plasma comprising helium, thereby forming a treated substrate. The treated substrate is then exposed to a second plasma selected from the group consisting of oxidizing plasmas and reducing plasmas. Next, a barrier layer is created on the treated substrate.

Abstract: Methods and apparatus are provided for semiconductor device (60, 95, 100, 106). The semiconductor device (60, 95, 100, 106), comprises a first region (64, 70) of a first conductivity type extending to a first surface (80), a second region (66) of a second, opposite, conductivity type forming with the first region (70) a first PN junction (65) extending to the first surface (80), a contact region (68) of the second conductivity type in the second region (66) at the first surface (80) and spaced apart from the first PN junction (65) by a first distance (LDS), and a third region (82, 96-98, 108) of the first conductivity type and of a second length (LBR), underlying the second region (66) and forming a second PN junction (63) therewith spaced apart from the first surface (80) and located closer to the first PN junction (65) than to the contact region (68). The breakdown voltage is enhanced without degrading other useful properties of the device (60, 95, 100, 106).

Abstract: A disclosed integrated circuit (IC) module includes an IC panel and multi level circuit structure, referred to as an IPD structure, overlying an upper surface of the IC panel. The IC panel includes an electrically conductive embedded ground plane (EGP), an integrated circuit (IC) die, and an encapsulating material. The EGP is a substantially planar structure that includes or defines a plurality of cavities. The EGP may include or define an IC cavity and an IPD cavity. The IC die may be positioned within the IC cavity such that a perimeter of the IC cavity surrounds the IC die. The IPD structure may define or include a passive device such as an inductor. The passive device may be positioned or located overlying the void in the EGP.

Abstract: A memory system including non-volatile memory cells. The memory system includes program circuitry that programs cells to a first threshold voltage or a second threshold voltage based on the number of times that cells of the memory system have been erased. In one embodiment, the threshold voltage is reduced when any set of cells of the memory system have been erased a specific number of times.

Abstract: A square wave to pseudo-sinusoidal clock conversion circuit comprises first and second stages. The first stage includes a cross-coupled differential pairs input gain stage having positive and negative input sides. Responsive to a differential square wave clock input, the first stage provides a first pass balanced differential clock with pull-up and pull-down symmetry. The second stage comprises positive and negative output side push-pull with low pass filter circuits, wherein the positive and negative output side push-pull with low pass filter circuits are responsive to the first pass balanced differential clock from the first stage for producing an output pseudo-sinusoidal clock that comprises a nearly sinusoidal output with slew rate controlled and clock waveform pull-up and pull-down symmetry for each of a respective one of the positive and negative output sides.

Abstract: A technique for increasing decoding reliability in an adaptive minimum mean squared error with successive interference cancellation (MMSE/SIC) decoder in a channel-coded multiple-input multiple-output (MIMO) communication system. A code block selector evaluates reliability metrics and determines whether the reliability metric of the decoded symbols of a particular indexed code block of a first code word satisfies a quality threshold. Depending upon this determination, a composite second code word is formed at each indexed code block using a previously calculated MMSE-LLR output of a second code word or a SIC-LLR output using the indexed symbols of a first code word. Composite second code word is decoded with increased accuracy.

Abstract: A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.

Abstract: Electrical supply apparatus comprising a start-up circuit element coupled to an output element for ensuring reliable start-up when first connected to a source of power. The start-up circuit element comprises first and second branches with current mirror coupling therebetween. The first branch comprises first and second transistors of opposite polarities for connection in series between the source of power and ground and a leakage path to ground in parallel with the second transistor for start-up current for the first transistor of the first branch in response to application of voltage from the source of power. The current mirror coupling between the first and second branches responds to start-up of the first transistor of the first branch to start up a first transistor of the second branch and provide start-up current to the output element.

Abstract: An integrated circuit package includes an integrated circuit die 1 having a plurality of optical elements 5 sensitive to and/or capable of generating light, whereby data communication to circuitry of the integrated circuit die can be effected using a data channels implemented using the plurality of elements. The data channels are along optical pathways provided by an adapter unit 17 mounted on a PCB 19. The adapter unit 17 forms the optical pathways between optical fibers 23 and the respective optical element 5. Thus, there is no requirement to implement expensive wire-bonding as part of the packaging process.

Abstract: A method for designing an integrated circuit, the method includes: providing an initial definition of a boundary scan register that includes identical super-cells adapted to be connected to multiple pin types; and determining the configuration of each super-cell by providing at least one pin type indication signal to each super-cell. An integrated circuit that includes a boundary scan super-cell, the boundary scan super-cell includes first circuitry adapted to be connected to at least one type of integrated circuit pin; characterized by further including a second circuitry, connected to first circuitry, wherein the second circuitry is adapted to receive at least one pin type indication signal and in response allows the boundary scan super-cell to be connected to at least one additional type of an integrated circuit pin.

Abstract: A localized content adaptive filter system including a tile buffer having an output providing first image information, a frequency analyzer providing a frequency information signal based on frequency content of the first image information, and an adaptive filter which is adjusted based on the frequency information signal. The frequency analyzer may include a wavelet transform filter and a frequency content analyzer. The adaptive filter may include filter select logic which receives the frequency information signal and second image information associated with the first image information, and which provides filtered image information. The filter select logic determines a filter based on the frequency information signal and the determined filter filters the second image information to provide the filtered image information.

Abstract: A method for generating an interleaved output during a decoding of a data block, the method includes: (i) selecting, in response to a row indicator, a row register and a multiplication factor to provide a selected row register and a selected multiplication factor; wherein the selected multiplication factor is responsive to a size of the data block; (ii) multiplying a value stored in the selected row register by the selected multiplication factor to provide an intermediate result; (iii) performing a modulo P operation on the intermediate result to provide a permutated result; wherein the permutated result and the value stored in the selected row register are adjacent elements of the same permutation; wherein P is responsive to a size of the data block; (iv) writing the permutated result to the selected row register; and (v) outputting a data block element that is selected in response to the permutated result.

Abstract: At least one adjustable gain analog amplifier (120, 124 and 128) in an analog line-up (102) amplifies by a gain an analog signal at an input of the analog line-up (102). The at least one adjustable gain analog amplifier (120, 124 and 128) is operable at one or more gains. At least one digital estimation device (134, 140 and 146) receives signal via an output (108) of the analog line-up (10) and provides a digital signal estimate representative of an analog signal at an input of a respective one of the at least one adjustable gain analog amplifier (120, 124 and 128) in the analog line-up (102). An AGC controller (152) monitors the digital signal estimate. The AGC controller (152) adjusts the gain of the at least one analog amplifier (120, 124 and 128). An RF receiver and an integrated circuit utilizing the novel features are also disclosed.

Abstract: A non-volatile memory cell and method for reading it are disclosed. In one embodiment, the non-volatile memory cell includes a fuse with a first terminal coupled to a first power supply voltage terminal, and a second terminal, a first transistor having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode, and a second transistor having a first current electrode connected to the first power supply voltage terminal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to the control electrode. By applying a read signal to the control electrode of the first transistor, the state of the cell (blown or unblown) is read.

Abstract: A wireless communication unit includes a baseband module and a radiofrequency module. A communication interface connects the baseband module to the radiofrequency module. Data can be communicated from the baseband module to the radiofrequency module and/or vice versa via the interface. The communication interface includes one or more data compression arrangement, for compressing original data to be transmitted over the communication interface, from a transmitting side of the communication interface to a receiving side of the communication interface, into compressed data and decompressing the compressed data after transmission and restoring the original data. The data compression arrangement may include a data compression unit at the transmitting side of the communication interface, and a data decompression unit at the receiving side of the communication interface.

Abstract: A digital clock generation circuit (200) and method of operation (400). A digital clock (250) produces an output (220) with a first frequency or a second frequency. A clock control circuit (204, 206) selectively sets the digital clock (250) to produce either the first frequency or the second frequency. An excess pulse counter (212) determines a number of pulses produced by the digital clock (250) at the second frequency that differs in the number of pulses that would have been produced at the first frequency, had the clock frequency change to the second frequency not occurred. An output phase correction circuit (230, 232, 212) removes, in response to the digital clock (250) changing from producing the second frequency to producing the first frequency, the number of pulses from the output (220) that were counted by the excess pulse counter (212).

Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (16) by selectively depositing an epitaxial silicon layer (70) to fill a trench (96), and then blanket depositing silicon to cover the entire wafer with near uniform thickness of crystalline silicon (102) over the epi silicon layer (70) and polycrystalline silicon (101, 103) over the nitride mask layer (95). The polysilicon material (101, 103) added by the two-step process increases the polish rate of subsequent CMP polishing to provide a more uniform polish surface (100) over the entire wafer surface, regardless of variations in structure widths and device densities. By forming first gate electrodes (151) over a first SOI layer (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon layer (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.

Abstract: A circuit includes a voltage regulator (208) for outputting a voltage at a regulated level, a protection circuit (260), and a load circuit (210) coupled to the voltage regulator. The protection circuit includes means for preventing the voltage regulator from outputting a voltage at a level higher than the regulated level during a start-up period of the voltage regulator.