Abstract: Power management in a light emitting diode (LED) system having a plurality of LED strings is disclosed. A voltage source provides an output voltage to drive a plurality of LED strings. An LED driver implements a feedback mechanism to monitor the tail voltages of the active LED strings to identify the minimum tail voltage and adjust the output voltage of the voltage source based on the lowest tail voltage. A loop calibration module of the LED driver calibrates the feedback mechanism of the LED driver based on a relationship between a digital code value used to generate a particular output voltage and another digital code value generated based on the minimum tail voltage resulting from the particular output voltage.

Abstract: A semiconductor device comprises a semiconductor layer, a body region of a first conductivity type formed in the semiconductor layer and extending from a first surface of the semiconductor layer, a first region of a second conductivity type formed in the body region, and a second region of the first conductivity type formed in the body region. The first region extends from the first surface of the semiconductor layer and provides a current electrode region of the semiconductor device. The second region surrounds the first region. The doping concentration of the first conductivity type in the second region is greater than a doping concentration of the first conductivity type in the body region.

Abstract: A capacitive device including at least one actuator structure formed on a substrate is provided. The capacitive device further includes a moveable structure formed on the substrate and mechanically coupled to the at least one actuator structure. The moveable structure includes a moveable capacitive plate and a bridge, formed substantially planar to the moveable capacitive plate. The bridge is used to mechanically and electrically couple the moveable capacitive plate to a signal line formed on the substrate such that the moveable capacitive plate moves up or down based on a force generated by the at least one actuator structure.

Abstract: A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material.

Abstract: A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.

Abstract: Integrated circuit packages are formed from a panel where the panel is separated by laser cutting the panel. In some embodiments, the panel is attached to the carrier for the formation of interconnect layers on the panel. Afterwards, the panel is cut with a laser while on the carrier to separate the integrated circuit packages. A tape or other type of structure may be attached to the top of the packages after the laser cutting. The integrated circuit packages are removed from the carrier by releasing the adhesive and removing the integrated circuit packages with the tape. The packages are then removed from the tape.

Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.

Abstract: Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained.

Abstract: A method (200) is described for an electronic assembly (30). An electronic die (24) with a sacrificial layer (28) on its back (27) and electrical contacts (26) on its front (25) is temporarily attached by its front (25) to a substrate (32). The back (27) is over-molded by a first material (34) extending over the substrate (32). The substrate (32) is removed leaving the die contacts (26) and the first material (33, 34) exposed. Interconnect layer(s) (44, 64) are provided over the first material (33, 34) and the die (24), electrically coupled to the contacts (26). Further components (66) can be coupled to the upper-most interconnects (64, 53). A second material (68) is over-molded over the components (66) and upper-most interconnects (64, 53). Thinning the first material (34) exposes the sacrificial layer (28) for removal.

Abstract: A method and a device, the device has ground voltage elevation compensation capabilities and includes: multiple current consuming components; a positive voltage supply input; a negative voltage supply input; and a compensation circuit, coupled to the negative voltage supply input and to a grounding element; wherein the compensation circuit is adapted to detect a ground voltage elevation resulting from a flow of excess consumption current through the grounding element, and in response couple the negative voltage supply input to the grounding element; wherein the excess current flows through the grounding element due to an increment in a current consumption of a current consuming element of the device.

Abstract: A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.

Abstract: A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further includes accessing the scribe grid pad to stimulate the die circuitry. A wafer includes a first die. The first die includes die circuitry, a plurality of conductive layers, and a bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality of conductive layers. The wafer includes a scribe grid having a scribe grid pad, and an interconnect electrically connecting the scribe grid pad to the die circuitry. The plurality of die of the wafer can then be singulated, and at least one of the singulated die can be packaged.

Abstract: A method of forming a semiconductor device includes providing a substrate for the semiconductor device. A base oxide layer is formed overlying the substrate by applying a rapid thermal oxidation (RTO) of the substrate in the presence of oxygen. A nitrogen-rich region is formed within and at a surface of the base oxide layer. The nitrogen-rich region overlies an oxide region in the base oxide layer. Afterwards, the semiconductor device is annealed in a dilute oxygen and hydrogen-free ambient of below 1 Torr partial pressure of the oxygen. The annealing heals bond damage in both the oxide region and the nitrogen-rich region in the base oxide layer. After annealing the semiconductor device in the dilute oxygen ambient, in-situ steam generation (ISSG) is used to grow and density the oxide region in the base oxide layer at an interface between the substrate and base oxide layer.

Abstract: A device for analyzing a fluid sample is provided. The device includes a substrate, a trench formed in said substrate, and a processor. The trench includes a channel, a sample chamber, and a reagent chamber, each in fluid communication with each another. The sample chamber is configured to receive the fluid sample. The processor is integrally formed in the substrate and is in communication with the trench. The processor is configured to analyze the fluid sample. Methods for manufacturing the device are also provided.

Abstract: A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

Abstract: A device for transmitting data in a wideband wireless network. The device may include a transmitter for transmitting data via a channel of the wideband wireless network, the transmitter is arranged to start the transmitting in response to a start signal. A first transmission controller is connected to the transmitter, for controlling transmission of data by the transmitter. The transmission controller includes an energy detector for detecting the amount of energy in the channel. The energy detector is arranged to repeat the detecting in response to a repeat signal. A comparator is connected to an output of the energy detector and to a control input of the transmitter. The comparator is arranged to compare the detected amount of energy with an energy threshold, to output the repeat signal to the energy detector in case the detected amount of energy exceeds the energy threshold; and to output the start signal to the transmitter when the detected amount of energy is below the energy threshold.

Abstract: The present invention provides a method for forming a transistor on a silicon substrate, the method comprising: providing a substrate comprising: a gate electrode with a liner comprising silicon and oxygen, and with a sidewall spacer, and source and/or drain region(s) in the substrate adjacent to the gate electrode, a layer at least 5 nm thick comprising silicon dioxide covering at least the source and/or drain regions; etching the layer comprising silicon and oxygen from at least the source and/or drain regions; and forming contacts for the source and/or drain region(s), characterized in that the layer comprising silicon and oxygen is etched from the substrate by steps comprising: forming an etchant from a plasma formed from a mixture comprising nitrogen trifluoride and ammonia; exposing the substrate to the etchant; and annealing the substrate.

Abstract: A method (20) of packaging integrated circuit dies (70) includes obtaining (22) a heat spreader substrate (24) having a top surface (38) with cavities (30) formed therein, each of the cavities (30) having a cavity floor (44). A surface (74) of each die (70) is attached (66) to one of the cavity floors (44) such that a surface (72) of each die (70) and the top surface (38) of the substrate (24) are coplanar. Build-up layers (88) with electrical interconnects (97) are formed (86) over the surface (72) of each die (80) and the surface (38) of the substrate (24) to form a panel (68) of IC dies (70). Following formation of the build-up layers (88), the panel (68) is separated (108) into multiple integrated circuit packages (28), each including electrical interconnects (97), a die (70), and the substrate (24) for dissipating heat away from the die (70) during operation.

Abstract: A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.

Abstract: A method for damage avoidance in transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled to happen within the buried strained layer in conjunction with the introduction of hydrogen.