Abstract: An instruction set is executed from Read Only Memory (ROM). When a current instruction in the instruction set corresponds to a reserved patch memory block of ROM, a Random Access Memory (RAM) index and a ROM return address are loaded into a memory map, and a program counter is set to a first reserved ROM address. After jumping the program counter to the first reserved ROM address, the program counter is jumped to RAM based on the RAM index to execute a patch code, which includes at least one instruction to set the program counter to a second reserved ROM address. When the program counter equals the second reserved ROM address, the ROM return address is retrieved. Then the instruction set is executed from ROM based on the ROM return address.

Abstract: A low drop out series regulator circuit for generating an output voltage that does not rely on voltage feedback or require a capacitor for stable operation includes first and second current sources connected in series between a supply voltage and ground. A resistor is connected between and in series with the first and second current sources, and a reference voltage is generated across the resistor by the current from the first current source. A first transistor is connected between the ground and a first node located between the resistor and the second current source. A current mirror circuit is connected between the supply voltage and the first transistor. A current sense transistor is connected between the current mirror circuit and an output terminal. An output transistor is connected between the supply voltage and the output terminal. The output voltage generated at the output terminal is equal to the reference voltage.

Abstract: In one embodiment of the present invention an interpreted language, such as, for example, Java, is selectively optimized by partitioning the interpreted language code (98) into a plurality of blocks (80-83) based on the complexity of each of the interpreted language instructions. In one embodiment of the present invention, each of the plurality of blocks is identified as either a block to be compiled into native code (80-82) if the block is simple, or a block to be interpreted (83) if the block is complex. The compiled and interpreted blocks are appended to form in-line mixed code (99) that contains both native code (90-92) and interpreted language code (93). This mixed code is formed before run-time, so that no further compilation is required at run-time. A processing unit (102) may be used to execute the native code directly without the use of a Java VM (10), while also executing, in-line, the interpreted language code (93) which requires use of the Java VM (10) to interpret the Java bytecodes.

Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

Abstract: An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.

Abstract: A power converter (10) includes a controller (12) configured to generate a switching signal. A first section (14) is coupled to the controller (12) and has first and second switches (26,30). The first section (14) is configured such that the first and second switches (26,30) operate in an alternating manner in response to the switching signal. A second section (16) is coupled to the controller (12) and has third and fourth switches (50,54). The second section (16) is configured such that the third and fourth switches (50,54) operate in an alternating manner in response to the switching signal. The first and second sections (14,16) are coupled to a node (88). A detection circuit (18) is coupled to the second section (16). The detection circuit (18) is configured to measure a voltage at the node between the operation of the third and fourth switches (50,54) and deactivate the second section when the voltage is above a predetermined threshold.

Abstract: A system and method for filtering a frame, the method includes: (i) processing, by a processing unit executing instructions, at least one portion of a frame to provide at least one processed frame portion; (ii) performing, by a hardware filter, deblocking filtering of the at least one processed frame portion to provide at least one filtered frame portion; and (ii) storing the at least one filtered frame portion in a memory unit that is accessible by the processing unit; whereas the stage of processing is responsive to previously filtered frame portions.

Abstract: Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively.

Abstract: A photolithographic mask is adapted for use in imparting a pattern to a substrate. The pattern comprises a plurality of features. At least one of the plurality of features (201) is implemented in the mask as a phase shifting structure (205) with a unitary layer of opaque material (207) disposed thereon. The mask is utilized to impart the pattern to a layer over a semiconductor substrate.

Abstract: A data converter for converting analog signals to digital signals, or for converting digital signals to analog signals is provided. In one embodiment, a production self-test is provided. In one embodiment, a high-speed lower-resolution method or mode for a data converter is provided. In one embodiment, a differential data converter with a more stable comparator common mode voltage is provided. In one embodiment, the input range of a digitally calibrated data converter is provided and maintained so that there is no loss in input range due to the calibration. In one embodiment, digital post-processing of an uncalibrated result using a previously stored calibration value is provided.

Abstract: At a particular stage in design of an integrated circuit, DFM improvements are identified which might conflict with design requirements applicable during a subsequent stage in the design flow. These DFM improvements are “reserved” that is, they are not implemented right away. However, an instance of a DFM-optimized version of this portion of the design is generated, characterized and stored. Meta information is associated with the reserved DFM improvements, for example locations in the design which correspond to the reserved DFM improvements are tagged. If, after the subsequent stage in the design flow, processing of the meta-information (tags) shows that the reserved DFM improvement does not actually conflict with the potentially-conflicting design requirement, the corresponding reserved DFM improvement is implemented, for example, by swapping-in the stored instance of the DFM-optimized version of this portion of the design.

Abstract: A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).

Abstract: A system and method Fast Fourier Transform (FFT) method in a multi-mode wireless processing system. The method can include loading an input vector into an input buffer, initializing a second counter and a variable N, where N=log2 (input vector size), and s is the value of the second counter, performing an FFT stage, and comparing s to N and performing additional FFT stages until s=N. Performing the FFT stage can include performing vector operations on data in the input buffer and sending results to an output buffer, the data in the input buffer comprising a plurality of segments, advancing the value of the second counter; and switching roles of the input and output buffers. The vector operations can include performing Radix-4 FFT vector operations on the four input data at a time and multiplying the resulting output vectors with a Twiddle factor.

Abstract: An interleaver for a turbo encoder and decoder comprising a first table populated with a first set of parameters to allow intra-row permutation of data within an array in accordance with a first wireless communication standard when operation in the first wireless communication standard is required and a second table populated with a second set of parameters to allow inter-row permutation of the data in accordance with the first wireless communication standard when operation in the first wireless communication standard is required wherein the first table is populated with a third set of parameters to allow intra-row permutation of data within an array in accordance with a second wireless communication standard when operation in the second wireless communication standard is required and to populate the second table with a fourth set of parameters to allow inter-row permutation of the data in accordance with the second wireless communication standard when operation in the second wireless communication standard i

Abstract: A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.

Abstract: A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.

Abstract: Oscillator devices and methods of operating such oscillator devices are disclosed. The oscillator devices include a current source, and an oscillation module to provide a clock signal. The frequency of the clock signal depends on the relationship between a threshold voltage of a transistor at the oscillation module and the current level provided by the current source. The transistor at the oscillation module is matched to a transistor at the current source so that the frequency of the clock signal is relatively insensitive to changes in device temperature.

Abstract: A data processing system uses a data processor instruction that forms an immediate value. The data processing instruction uses a first field as a portion of the immediate value. A second field of the data processing instruction determines a positional location of the portion of the immediate value within the immediate value. A bit value in a third field of the data processing instruction is used to determine a remainder of the immediate value.

Abstract: A device having protection capabilities, the device includes a voltage supply unit that is connected to an integrated circuit and provides a supply voltage to the integrated circuit; wherein the integrated circuit includes: a security real time clock generator that includes an input; a masking unit that is connected to the input, wherein the masking unit isolates the input when a voltage supply monitor is disabled; and wherein the voltage supply monitor monitors the voltage supply unit and wherein a change in a level of supply voltage affects a level of a signal provided to the input.