Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract: A self-poling piezoelectric based MEMS device is configured for piezoelectric actuation in response to application of a device operating voltage. The MEMS device comprises a beam, a first electrode disposed on the beam, a layer of piezoelectric material having a self-poling thickness disposed overlying a portion of the first electrode, and a second electrode overlying the layer of piezoelectric material. The layer of piezoelectric material is self-poled in response to application of the device operating voltage across the first and second electrodes. In addition, the self-poled piezoelectric material has a poling direction established according to a polarity orientation of the device operating voltage as applied across the first and second electrodes.

Abstract: A control generator is provided, comprising: a summer configured to add a ramping phase adjustment signal and a basic phase adjustment signal to generate a combined phase adjustment signal based on the combined phase adjustment signal; a look-up table configured to generate first through Nth digital phase and frequency adjustment signals; and first through Nth digital to analog converters configured to convert the first through Nth digital phase and frequency adjustment signals to first through Nth analog phase and frequency adjustment signals in accordance with first through Nth clock signals, respectively. wherein N is an integer greater than 1.

Abstract: A video processing system may include a video input and a video output for outputting manipulated video images. The system may have a video processing chain connecting the video input to the video output. The chain may include a series connection of two or more video processing components. The components may each include a component input for receiving video images and a component output for outputting processed video images. A control input may be present for controlling the video processing component to be in an enabled or a disabled state. The video processing component may be arranged to obtain in the enabled state the processed video images by performing a respective processing operation on the received video images; and to obtain in the disabled state the processed vide images by forwarding the received video images to the component output without performing the processing operation.

Abstract: A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

Abstract: In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed.

Abstract: A semiconductor device is formed using a semiconductor substrate. A gate dielectric is formed over the semiconductor substrate. A gate electrode layer is formed over the gate dielectric. A patterned masking layer is formed over the gate electrode layer. A first region of the gate electrode layer lies within an opening in the patterned masking layer. The first region of the gate electrode layer is partially etched to leave an elevated portion of the gate electrode layer and a lower portion adjacent to the elevated portion. A sidewall spacer is formed adjacent to the elevated portion and over the lower portion. An implant is performed into the semiconductor substrate using the elevated portion and the sidewall spacer as a mask. The sidewall spacer and the lower portion are removed.

Abstract: An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth.

Abstract: An integrated circuit (IC) module (20) includes a ground plane (22) having adjoining cutouts (30, 32). The cutout (32) defines a critical signal pathway (38). A device (24) is positioned in the cutout (30) and a device (26) is positioned outside of the cutout (30) adjacent to the cutout (32). An electrical interconnect (56) positioned in the critical signal pathway (38) interconnects the device (24) with the device (26). A method (60) of packaging the IC module (20) entails encapsulating the ground plane (22) and devices (24, 26) in a packaging material, and forming conductive vias (92) in the packaging material (84) that extend between the ground plane (22) and an exterior surface (94) of the packaging material (84). The conductive vias (92) surround the device (24) and cutout (32) to protect again electromagnetic interference and to provide guided signal pathways for high frequency signals on electrical interconnect (56).

Abstract: An integrated circuit comprises electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to one or more external connector(s) of the integrated circuit. The ESD protection circuitry comprises at least one ESD protection component coupled to the one or more external connectors for providing ESD protection thereto. The ESD protection circuitry further comprises an ESD connector, coupled to the one or more external connector(s), arranged to couple supplementary ESD protection to the one or more external connector(s).

Abstract: A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls (44, 46) in a semiconductor substrate (20) having first and second opposing surfaces (22, 24). An inductor (56) is formed on the first surface (22) of the semiconductor substrate (20) and a hole (60) is formed through the second surface (24) of the substrate (20) to expose the substrate (20) between the first and second lateral etch stop walls (44, 46). The substrate (20) is isotropically etched between the first and second lateral etch stop walls (44, 46) through the etch hole (60) to create a cavity 62) within the semiconductor substrate (20). A sealing layer (70) is formed over the etch hole (60) to seal the cavity (62).

Abstract: A circuit includes a voltage regulator (208) for outputting a voltage at a regulated level, a protection circuit (260), and a load circuit (210) coupled to the voltage regulator. The protection circuit includes means for preventing the voltage regulator from outputting a voltage at a level higher than the regulated level during a start-up period of the voltage regulator.

Abstract: A linear voltage regulator includes a first transistor, a feedback circuit, and a control circuit. The first transistor includes a first terminal coupled to an input terminal of the regulator, a second terminal coupled to an output terminal of the regulator, and a control terminal. The first transistor is configured to provide a load current to the output terminal at a desired voltage level based on a control signal on the control terminal. The feedback circuit is coupled to the output terminal and is configured to generate a feedback signal based on an actual voltage level at the output terminal. The control circuit is configured to provide, based on the feedback signal, the control signal at a level to substantially maintain an output voltage at the output terminal at the desired voltage level. An operating current of the control circuit is configured to increase, by a limited amount, responsive to a transient increase in the load current.

Abstract: A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first and second opposing inner walls (74, 76) and a floor (78). First and second conductive plates (106) may be formed over the first and second opposing inner walls (74, 76) of the isolation trench (62) respectively such that there is a gap (90) between the first and second conductive plates (106). First and second semiconductor devices (114) may be formed in the semiconductor substrate on opposing sides of the isolation trench (62). The method may include forming a trench (62) in a semiconductor substrate, forming first and second conductive plates (106) within the trench, and forming first and second semiconductor devices (114) in the semiconductor substrate on opposing sides of the trench (62).

Abstract: Apparatus are provided for a stacked cascode current source. An apparatus is provided for an electrical device comprising an input node and an output node. A first transistor stack is coupled to the input node. The first transistor stack includes a first transistor and a second transistor. A drain terminal and a gate terminal of the first transistor are coupled to the input node. A drain terminal of the second transistor is coupled to a source terminal of the first transistor and a gate terminal of the second transistor is coupled to the input node. A second transistor stack coupled to the first transistor stack and the output node to create a current mirror for the first transistor stack.

Abstract: A method is provided for receiving a data frame in an ultrawide bandwidth network. In this method, a device receives an ultrawide bandwidth signal containing a data frame. The device then performs an acquisition operation during a first preamble in the data frame, and identifies a marker after the first preamble that indicates that the first preamble has ended. After this, the device performs a signal processing operation during a second preamble in the data frame. After the training, the device then receives a header in the data frame, and then receives a payload in the data frame. By having a marker between the two preambles, this method provides a receiving device with critical information regarding the timing of the preamble section of a frame.

Abstract: In a GSM/EDGE Single Antenna Interference Cancellation (SAIC) operation environment, a mobile station is required to operate in a wide range of interference levels. An SAIC linear equalizer that takes advantage of the GMSK signal structure performs better than a conventional Maximum Likelihood Sequence Estimation (MLSE) equalizer in high interference levels, while it performs worse in low interference levels. A dynamic selection between the SAIC linear equalizer and the MLSE equalizer for each received burst is achieved to provide the optimal performance across the entire required operation environments. The dynamic selection is based on the estimated noise plus interference energy relative to the total received signal energy. The soft information calculated by the two categories of equalizers is properly scaled to generate soft information with balanced magnitude.

Abstract: A method of transitioning between an active mode and a power-down mode in a processor-based system includes saving a state of the active mode, detecting the occurrence of one or more interrupt events during a transition between the active mode and the power-down mode, and responding to the detected interrupt events.

Abstract: An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.

Abstract: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.