Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Abstract: A spool braking device and a spool braking method for increasing spool braking capability. The spool braking device includes a reel attached to a fishing rod in a detachable manner. A rotatable spool is arranged in the reel. A fishing line is wound to the spool. A brake mechanism electronically brakes rotation of the spool. An acceleration sensor detects swing acceleration produced when the fishing rod is swung and generates an acceleration signal. A brake control unit determines whether or not the spool needs to be braked based on the acceleration signal and drives the brake mechanism.

Abstract: A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.

Abstract: Methods are provided for forming Quad Flat No-Lead (QFN) packages. An embodiment includes disposing an active side of a semiconductor chip on a plurality of leads, coupling a plurality of wire bonds to the active side of the semiconductor chip, coupling the plurality of wire bonds to the plurality of leads in a space between the active side and the plurality of leads, and encasing the semiconductor chip, at least a portion of each of the plurality of leads, and the plurality of wire bonds in a mold material to define a mounting side of the QFN package. The mounting side has a perimeter, the plurality of leads are oriented on and exposed on the mounting side within the perimeter, and the plurality of wire bonds are oriented between the active side and the mounting side within the mold material.

Abstract: A method of forming a semiconductor device comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate, forming a first region of the first conductivity type in the semiconductor layer, and forming a control region over the semiconductor layer and over part of the first region. A mask layer is formed over the semiconductor layer and outlines a first portion of a surface of the semiconductor layer over part of the first region. Semiconductor material of a second conductivity type is provided to the outlined first portion to provide a second region in the semiconductor layer.

Abstract: Latch-up of CMOS devices (20, 20?) is improved by using a structure (40, 40?, 80) having electrically coupled but floating doped regions (64, 64?; 65, 65?) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64?; 65, 65?) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64?) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55?) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions.

Abstract: A wireless communication device comprises a number of sub-systems and clock generation logic arranged to generate at least one clock signal to be applied to the number of sub-systems. One of the number of sub-systems comprises sampling logic for receiving input data and performing initial sampling on an input data bit using multiple separated phases of a clock period of the at least one clock signal applied to the sampling logic thereby producing multiple phase separated sampled outputs of the input data bit. The sampling logic is configured to perform a number of re-sampling operations on the multiple phase separated sampled outputs at a number of intermediate phases thereby producing multiple phase separated intermediate sampled outputs prior to performing a final sample of the multiple phase separated intermediate sampled outputs at a single phase of the at least one clock signal to produce a sampled input data signal.

Abstract: A method of managing the power up of a device that has power down state; and at least two power up states, wherein the method includes the following steps: statistically analysing the power up time profile of the device; determining one or more predetermined statistical indicators associated with the stored power up time profile; calculating an anticipated start up time from the statistical indicators; at the anticipated start up time changing the device state from the power down state to a pre-determined one of the power up states depending on the statistical indicators; maintaining the device at pre-determined power up states for a predetermined duration; returning the device to the power down state if there is no user interaction with the device during the predetermined duration.

Abstract: A device and a method. The device includes: (i) a processor, connected to the receiver, (ii) an interface adapted to receive a test vector and to output a test response, the test vector includes a first group of signals that include idle signals and at least one information frame and a second group of signals that include timing signals and data signals; and (iii) a receiver, connected to the interface. The receiver is adapted to receive the first group of signals and filter out the idle signals and at least one instruction frame delimiters to provide at least one instruction. The device is adapted to send the at least one instruction to at least one instruction buffer. The processor is adapted to execute at least one instruction stored in the at least one instruction buffer and to respond to the second group of signals such as to provide test responses.

Abstract: A microelectromechanical systems (MEMS) transducer (90) is adapted to sense acceleration in mutually orthogonal directions (92, 94, 96). The MEMS transducer (90) includes a proof mass (100) suspended above a substrate (98) by an anchor system (116). The anchor system (116) pivotally couples the proof mass (100) to the substrate (98) at a rotational axis (132) to enable the proof mass (100) to rotate about the rotational axis (132) in response to acceleration in a direction (96). The proof mass (100) has an opening (112) extending through it. Another proof mass (148) resides in the opening (112), and another anchor system (152) suspends the proof mass (148) above the surface (104) of the substrate (98). The anchor system (152) enables the proof mass (148) to move substantially parallel to the surface (104) of the substrate (98) in response to acceleration in at least another direction (92, 94).

Abstract: A method of forming devices including forming a first region and a second region in a semiconductor substrate is provided. The method further includes forming a semiconductive material over the first region, wherein the semiconductive material has a different electrical property than the first semiconductor substrate, forming a first dielectric material over the first region, depositing a second dielectric material over the first dielectric material and over the second region, wherein the second dielectric material is different than the first dielectric material, and depositing a gate electrode material over the high dielectric constant material. In one embodiment, the semiconductive material is silicon germanium and the semiconductor substrate is silicon.

Abstract: A transceiver module can share a common connector with a rechargeable battery connection. The transceiver module can be protected from the high voltages applied by a battery charger. Determining when the voltage applied at a connector exceeds a reference voltage and electrically decoupling the transceiver module from the connector when the reference voltage is exceeded can protect the transceiver module. The reference voltage can be set at a level so that the transceiver is decoupled from the connector when the voltage at the connector reaches a voltage that is unsafe for the transceiver.

Abstract: A series regulator with fold-back over current protection has a high ratio current mirror circuit located between a sense transistor and its voltage output terminal. The series regulator receives an input voltage at an input terminal and generates a stable output voltage at an output terminal. A first amplifier receives a reference voltage. An output transistor is connected between the input terminal and the output terminal and has a gate connected to an output of the first amplifier. A current limiting transistor and the current sense transistor are connected to the input terminal, the output terminal of the first amplifier, and the gate of the output transistor. A voltage divider, connected between the output terminal and ground, generates first and second voltage signals. The first voltage signal is provided to a non-inverting input of the first amplifier. A first current source is connected to the voltage divider and receives the second voltage signal.

Abstract: Systems and methods for monitoring and controlling the operation of extreme ultraviolet (EUV) sources used in semiconductor fabrication are disclosed. A method comprises providing a semiconductor fabrication apparatus having a light source that emits in-band and out-of-band radiation, taking a first out-of-band radiation measurement, taking a second out-of-band radiation measurement, and controlling the in-band radiation of the light source, at least in part, based upon a comparison of the first and second out-of-band measurements. An apparatus comprises a detector operable to detect out-of-band EUV radiation emitted by an EUV plasma source, a spectrometer coupled to the electromagnetic detector and operable to measure at least one out-of-band radiation parameter based upon the detected out-of-band EUV radiation, and a controller coupled to the spectrometer and operable to monitor and control the operation of the EUV plasma source based upon the out-of-band measurements.

Abstract: A radio frequency device comprises a radio frequency (RF) power amplifier (PA) operably coupled to a protection circuit for minimising voltage standing wave ratio effects, wherein the protection circuit comprises a current limiter indexed to a power supplied to the RF PA. In this manner, the protection circuit combines detection of both current and voltage increase in order to provide a direct feedback on the final RF PA stage via a bias control.

Abstract: A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an isolation signal. In response to a reference voltage supplied to the latch being restored to a normal operating voltage, indicating that the integrated circuit has transitioned from the low-power mode to a normal mode, a data restoration circuit provides the retained data at the output of the latch prior to negation of the isolation signal. This reduces the likelihood that a delay in negation of the isolation signal will result in the latch output providing incorrect data, thereby reducing the likelihood of the latch output causing errors in downstream elements of the integrated circuit.

Abstract: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

Abstract: A reference circuit comprises a first current generator comprising a first transistor operably coupled to a second transistor and having respective base current corresponding to a positive temperature dependence of the reference circuit. A resistance is operably coupled to the first current generator and arranged to provide a second current corresponding to a negative temperature dependence of the reference circuit. A second current generator is operably coupled to the resistance and the first current generator that generates a combined current as a sum of the second current and base current. In this manner, the output voltage of the curvature compensated voltage and/or current reference circuit is substantially linear and substantially independent of the operating temperature of the circuit.

Abstract: Apparatus and systems are provided for a single amplifier filter capable of a high quality factor. A filter comprises an amplifier having an amplifier input and an amplifier output, wherein the amplifier is configured to produce an output signal at the amplifier output based on a signal at the amplifier input. A first resistive element is coupled between an input node and the amplifier input, a second resistive element is coupled between a first node and the amplifier input, and a third resistive element is coupled between the amplifier output and the first node. A first capacitive element is coupled between the amplifier output and the amplifier input. The filter comprises a second node for an inverse of the output signal, wherein a second capacitive element is coupled between the first node and the second node.

Abstract: A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behaviour, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine.