Abstract: An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.

Abstract: An improved lateral bipolar electrostatic discharge (ESD) protection device (40) comprises a semiconductor (SC) substrate (42), an overlying epitaxial SC layer (44), emitter-collector regions (48, 50) laterally spaced apart by a first distance (52) in the SC layer, a base region (54) adjacent the emitter region (48) extending laterally toward and separated from the collector region (50) by a base-collector spacing (56) that is selected to set the desired trigger voltage Vt1. By providing a buried layer region (49) under the emitter region (48) Ohmically coupled thereto, but not providing a comparable buried layer region (51) under the collector region (50), an asymmetrical structure is obtained in which the DC trigger voltage (Vt1DC) and transient trigger voltage (Vt1TR) are closely matched so that |Vt1TR?Vt1DC|˜0.

Abstract: A circuit and method reduces disturb in a memory array resulting from one of two supply voltages dropping below a predetermined value. Memory control logic is operated using a logic power domain. Higher voltages than that of the logic power domain are generated in response to an oscillator oscillating. The higher voltages are used to operate the memory array. Operation of the oscillator is controlled with the memory control logic when the logic power domain is at least at a first level or value. The oscillator is disabled when the logic power domain is below the first level. The disabling of the oscillator has the effect of preventing generation of the higher voltages. This facilitates preventing the higher voltages from reaching the memory array when they may not be properly controlled.

Abstract: A device enabling simple detection of a recording medium placed on a tray includes at least two electrodes arranged on the tray, an electric field sensor connected to the electrodes, and a control circuit connected to the electric field sensor. The electric field sensor detects capacitance in accordance with the distance between the electrodes relative to the recording medium placed on the tray. The control circuit determines the recording media type of the recording medium based on the capacitance detected by the electric field sensor.

Abstract: A system and method for EVM self-testing a communication device is provided including receiving (305) a complex waveform, sampling (310) first and second sample voltages from the complex waveform, selecting (315) first and second ideal voltages from I- and Q-arrays, and determining (320) an error vector by comparing the first and second sample voltages with the first and second ideal voltages for a desired number of comparisons (N). The first ideal voltage corresponds with the first sample voltage, the second ideal voltage corresponds with the second sample voltage, and the I- and Q-arrays are derived from a conversion of a bitstream to the complex waveform.

Abstract: An application processor circuit has SD-compatible interface protocols and can perform both host and slave functions. The circuit includes SD bus interface logic for realizing SD interface signals defined in SD-compatible interface protocols; system bus interface logic for performing the interface function on the system bus side; a data buffer for adjusting the data transfer rate difference between the SD bus interface and the system bus interface; a data buffer controller for controlling access to the data buffer; and a configuration unit for configuring the circuit to work in the host mode or slave mode. The SD-compatible interface protocols include MMC/SD/SDIO protocol, high speed MMC/SD/SDIO protocol, and CE-ATA interface protocol. The SD host logic and slave logic are incorporated in a single module to support both the SD host and slave functions, so as to achieve more convenient data transfer between electronic devices.

Abstract: A method is provided for forming a microelectronic assembly. A contact structure (46) is formed over a first side of a first substrate (20) having a microelectronic device formed over a second side thereof. The contact structure is electrically connected to the microelectronic device. A non-solderable layer (52) is formed over at least a portion of the contact structure and at least a portion of the first substrate. The contact structure and a second substrate (62) are interconnected with solder (68).

Abstract: A sensor with continuous self test (101). An exemplary inertial sensor (106) may include one or more self test electrodes (208, 210) so that one or more test signals (402, 404) may be applied to the electrodes (208, 210) during normal operation of the sensor. Normal sensor output may be read and stored (316) during normal operation, when self test signals are typically not applied to the sensor. The normal sensor output provides a baseline for comparison to a sensor offset error detection signal (408) produced when a test signal may be applied to one self test electrode, and also to a sense error detection signal (406) produced when a test signal may be applied to both self test electrodes (208, 210).

Abstract: A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater includes a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change material. In some embodiments, a method includes forming a electrode layer over a substrate, depositing a first layer, providing nanoclusters over the first layer, and etching the first layer. The first layer comprises one of a group consisting of a heater material and a phase change material. The first layer may be etched using the nanocluster defined pattern to form pillars from the first layer.

Abstract: An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Abstract: A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best electromigration quality value is selected. In one embodiment, each routing is analyzed with attention to the current that passes through each of the routing's segments in order to compute a current distribution that is used to compute a routing quality vector. In another embodiment, multiple placements are generated and the electromigration placement quality vectors are computed for the various placements with the placement with the best electromigration quality vector being selected. In one embodiment, the placement with the best electromigration quality vector is routed the number of times to determine the routing with the lowest (best) electromigration quality value.

Abstract: A signal generation power management control system (100) for use in a portable communications device includes a digital signal processor (DSP) (101) for processing a digital source input and providing a digital processed bit stream A digital-to-analog converter (DAC) (103) is used for converting the digital processed bit stream to provide an analog signal. A power management controller (115) within the DSP (101) is then used for interpreting control parameters of signal processing components used within the portable communications device and dynamically adjusting the bias current of these components based on minimal signal requirements of the analog signal.

Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.

Abstract: A method for mitigating interference from a switched-mode power supply begins by comparing a channel of interest of a plurality of channels with a switching rate of a switch-mode power supply. The method continues when the channel of interest compares unfavorably to the switching rate by adjusting the switching rate of the switch-mode power supply until the channel of interest compares favorably to the switching rate.

Abstract: A power supply controller for a plurality of lighting components in a battery-powered apparatus. The power supply controller comprises a current source common to the lighting components, and a sequencer for coupling the current source sequentially to each of the lighting components with a repetition rate substantially faster than the flicker perception rate. Each of the lighting components comprises a respective array of lighting elements connected in series to receive the same current as the other lighting elements of the same lighting component.

Abstract: Method and apparatus for designing an integrated circuit by providing an IC layout design. Adding one or more assist features to the IC layout design. Identifying which of the one or more added assist features in the IC layout design will cause one or more defects in the resultant wafer die manufactured from the IC layout design. Amending the one or more identified assist features.

Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.

Abstract: A mixed signal device for use in a distributed system of independent and interoperating devices, comprising at least one analog module, characterised in that the mixed signal device further comprises a diagnosis controller coupled to the at least one analog module, said diagnosis controller being operable to determine an operational status of the mixed signal device.

Abstract: A read only memory implemented as a 3D integrated device has a first stratum, a second stratum, and bonded inter-strata connections for coupling the first stratum to the second stratum. The physical bonding between the two strata implements the programming of the read only memory. The stratum may be in wafer form or in die form. The first stratum includes functional active devices and at least one non-programmed active device. The second stratum includes at least conductive routing to be associated with the at least one non-programmed active device. The bonded inter-strata connections include at least one bonded programmable inter-strata connection for programming the at least one non-programmed active device and for providing conductive routing to the programmed active device. The two strata thus form a programmed ROM. Other types of programmable storage devices may be implemented by bonding the two strata.

Abstract: A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch.