Abstract: A device (100) for locating an end of a received frame, the device comprises: at least one memory unit (120) for storing path metrics; at least one processor, adapted to: provide hypothetical trellis paths that end at different possible end points; perform, for each hypothetical trellis path, a forward detection check; calculate a false detection variable for hypothetical trellis paths that passed the forward check; and determine the end point of the received frame in response to the calculations. Wherein the calculation of the forward detection check is much faster than the calculation of the false detection variable.

Abstract: A motion stabilization system including a filter bank and motion stabilization logic. The filter bank receives a video signal and provides at least one high frequency sub-band signal which includes edge information of the video signal. The motion stabilization logic receives the high frequency sub-band signal, a reference image, and the video signal and provides a stabilized image. The reference image is generated from image stabilization information developed during motion processing. The motion stabilization system may include an edge detector which receives and binarizes the high frequency sub-band signal. Binarization significantly reduces the amount of information to be processes by the motion stabilization logic. The motion stabilization system may further include a tile buffer which stores a portion of the video signal and which provides a video signal portion to the filter bank. The filter bank may be implemented as a discrete wavelet transformation filter.

Abstract: A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.

Abstract: In an orthogonal frequency division multiplex communication system, for example a HIPERLAN/2 system, power amplifiers (224) of mobile terminals (4, 6) are switched off when not in use, and then switched on again when a signal transmission is to be made. This conserves power, but introduces a power amplifier transient (315). An access point (2), i.e. a type of base station, compensates for these power amplifier transients (315) using a simple scalar constant gain transient correction, over a full OFDM symbol (or a plurality of OFDM symbols). The correction is updated on an OFDM symbol by symbol basis (or plurality of symbols by plurality of symbols basis).

Abstract: A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate (228) and a bottom gate (240); (b) creating first, second and third openings in the semiconductor structure, wherein the first opening exposes a portion of the bottom gate; (c) filling the first, second and third openings with a conductive material, thereby forming source (258) and drain (260) regions in the second and third openings and a conductive region (253) in the first opening; and (d) forming an electrical contact (278) to the conductive region.

Abstract: A method and device for managing retransmit operations. The device, includes a FIFO memory unit, a read pointer, a retry pointer and a write pointer. The device is characterized by including a gray code state machine connected to an emulated read pointer logic; whereas the gray code state machine is adapted to provide a gray code word representative of a state of a read logic that comprises the read pointer; whereas the emulated read pointer logic is adapted to process at least one gray code word and to provide an emulated read pointer that tracks a FIFO memory unit entry that stores data that was not accepted; whereas the emulated read pointer logic is connected to a write control logic adapted to control writing operations to the FIFO memory unit in response to the emulated read pointer logic; and whereas the read logic receives a read clock that differs from a write clock provided to the emulated read pointer logic and to the write control logic.

Abstract: A method is provided for detecting a stall condition in a stepping motor. The stepping motor has two coils and a rotor, and is micro-stepped by substantially continuously driving both of the two coils with out-of-phase time varying voltages. The method includes stepping the stepping motor to a next micro-step. It is then determined when a predetermined motor parameter of a first coil of the two coils is to be sampled. To sample the predetermined motor parameter of, for example, the first coil, the first coil is opened for a predetermined period, wherein the predetermined period is less than or equal to a micro-step. Then the first coil is sampled during the predetermined period and the result of sampling is integrated and used to increment or decrement an accumulated value. If the accumulated value is less than a preset value, then a stall condition exists.

Abstract: A method for signal strength detection begins by comparing a signal strength representation of a signal with a signal strength representation of a reference signal. The method continues by adjusting, when the signal strength representation of the signal compares unfavorably with the signal strength representation of the reference signal, at least one of the signal strength representation of the signal and the signal strength representation of the reference signal until the signal strength representation of the signal compares favorably with the signal strength representation of the reference signal. The method continues by determining signal strength of the signal based on the adjusting of the signal strength representation of the signal and signal strength of the reference signal.

Abstract: An annular trench region is formed at a semiconductor substrate of an electronic device that defines a conductive plug of the through-wafer via, wherein the conductive plug includes an undisturbed portion of the semiconductor substrate.

Abstract: A memory includes a bit cell array including a plurality of word lines and address decode circuitry having an output to provide a predecode value. The address decode circuitry includes a first plurality of transistors having a first gate oxide thickness. The memory further includes word line driver circuitry having an input coupled to the output of the address decode circuitry and a plurality of outputs, each output coupled to a corresponding word line of the plurality of word lines. The word line driver includes a second plurality of transistors having a second gate oxide thickness greater than the first gate oxide thickness. A method of operating the memory also is provided.

Abstract: A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack includes depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers includes performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers includes depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer includes pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.

Abstract: A memory device includes a latch component including a first input configured to receive a functional data bit associated with a functional operation, a second input configured to receive a memory test/repair data bit associated with a memory test operation, and a latch comprising a data input and a data output and select logic configured to selectively connect one of the first input or the second input to the data input of the latch based on a mode of operation of the memory device. A method includes operating a memory device in a first mode associated with a memory test operation and in a second mode associated with a functional operation. The method further includes storing a memory test/repair data bit at a latch component of the memory device in the first mode and storing a functional data bit at the latch component in the second mode.

Abstract: A system includes a master device and a plurality of slave devices. The master device initiates a bus transaction having an arbitration data field for processing by a subset of the slave devices. Each slave device of the subset arbitrates a corresponding data value for the arbitration data field via the multiple-access bus such that an extreme data value of the data values of the slave devices of the subset is transmitted via the multiple-access bus for the arbitration data field. The slave device can arbitrate its data value by providing the data value for serial transmission via a data line of the multiple-access bus and monitoring the data line. In response to determining that a bit value of the data value being provided does not match the state of the data line, the slave device terminates provision of the data value, thereby ceasing arbitration of its data value.

Abstract: An electronic device can include a substrate including a first trench having a first bottom and a first wall. The electrode device can also include a first gate electrode within the first trench and adjacent to the first wall and overlying the first bottom of the first trench, and a second gate electrode within the first trench and adjacent to the first gate electrode and overlying the first bottom of the first trench. The electronic device can further include discontinuous storage elements including a first set of discontinuous storage elements, wherein the first set of the discontinuous storage elements lies between (i) the first gate electrode or the second gate electrode and (ii) the first bottom of the first trench. Processes of forming and using the electronic device are also described.

Abstract: A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range.

Abstract: A wireless communication unit comprises a frequency generation circuit employing a phase locked loop (PLL) circuit comprising a voltage controlled oscillator having a modulation port for directly modulating a signal output from the voltage controlled oscillator. The voltage controlled oscillator is operably coupled to at least one switch and a capacitor bank comprising one or more varactors. A controller is arranged to switch in one or more varactors associated with the modulation port of the phase locked loop circuit to provide an inverse cubic relationship to the direct modulated signal. In addition, or alternatively, the phase locked loop (PLL) circuit may comprise a voltage controlled oscillator having a tuning port for controlling a frequency of a signal output from the voltage controlled oscillator. The controller here is arranged to switch in one or more varactors associated with the tuning port of the phase locked loop circuit in an inverse square relationship.

Abstract: A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.

Abstract: A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.

Abstract: A method of searching digital communication signals in a system includes combining a plurality of channel measurements, providing output of the combining of channel measurements as an added input to the plurality of channel measurements, and acquiring a signal symbol based on results from the combining of channel measurements without addressing all timing hypothesis individually via a correlation operation.

Abstract: A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.