Abstract: A carrier tape (10) for electronic components or devices (44) includes a tape body (12) and a plurality of pockets (14) formed in the tape body (12). Each of the pockets (14) includes a sidewall (18) and a base portion (20). The base portion (20) joins the sidewall (18) at an edge portion (22). A protrusion (24) is formed in the base portion (20) of the pocket (14). The protrusion (24) is configured to maintain a separation between the edge portion (22) and a surface on which the pocket (14) rests.

Abstract: An ultra-wide band (UWB) waveform encoding method is provided. The method includes receiving a data stream; generating a first encoder signal and a second encoder signal such that if the first and second encoder signals were mixed, the mixing would return a representation of the data stream; generating a sequence of pulses; mixing the first encoder signal with at least a portion of the sequence of pulses, to produce a mixing result; and mixing the second encoder signal with the mixing result, to produce a sequence of ultra wideband wavelets encoded in accordance with the data stream.

Abstract: A method (600) for controlling a transmit power of an interface module (230) is provided. The method includes generating a transmit power code at a power code generator (240) (610); receiving the transmit power code at the interface module (620); receiving control signals at the interface module (650); and generating a transmit signal at a transmitter circuit (410) in the interface module based on the control signals and the transmit power code (660). In this method, the power level of the transmit signal is controlled by the transmit power code, and the transmitter circuit and the power code generator are formed on separate circuit elements.

Abstract: A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.

Abstract: An electronic switch circuit includes an electronic switch having a first terminal, a second terminal and a third terminal, control means for applying to the first terminal a cyclic drive waveform which causes the electronic switch to conduct between the second and third terminals during a selected portion of each cycle of the waveform, operably coupled to the control means to control synchronisation of the cyclic drive waveform a detector operable to detect a change of direction of current flow at the second terminal of the electronic switch and means for monitoring and, where required, compensating for offset error of the detector. The electronic switch may beneficially be a synchronous rectifier. The synchronous rectifier may be used in DC-DC power converters to improve efficiency.

Abstract: Embodiments of the present invention relate generally to receivers. A frequency modulated (FM) receiver includes an equalizer control unit coupled to receive at least one FM signal quality indicator and provide a control signal based on the FM signal quality indicator. An adaptive equalizer coupled to receive the control signal from the equalizer control unit and an FM signal and provide a filtered FM signal corresponding to the received FM signal. Coefficients of the adaptive equalizer are reset in response to the control signal. Another embodiment relates to a method for processing a frequency modulated (FM) signal. An FM signal is received. At least one FM signal quality indicator is used to provide a control signal. Based on the control signal, the received FM signal is filtered using one of an adaptive filter and a static filter to provide a filtered FM signal.

Abstract: A semiconductor power network (100) decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires (420)) to be made to the network (100). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and/or added decap can be distributed throughout a violation region (120) of the semiconductor circuit (100) design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level (220).

Abstract: The present invention provides a method to adjustably sample a first digitized signal having a first data rate to produce a second digitized signal having a second data rate. This involves processing the second digitized signal to produce an output signal having a timing component contained therein. An error sensing module determines a timing error between the timing component and a digitized reference period. Then this timing error is used to produce a feedback signal that is applied to the sample timing of the first digitized signal. This allows the second digitized signal to be processed using a time domain associated with the second data rate.

Abstract: A PWM generation module generates a PWM data signal used to control a light emitting diode (LED) driver for one or more strings of LEDs of a display device. The PWM data signal is synchronized with the frame boundaries of the video content being displayed. The PWM generation module can configure the PWM data signal such that a new PWM cycle is initiated at the start of each successive frame, and further whereby those PWM cycles that would be prematurely terminated at frame boundaries are instead driven at a constant reference level until the frame boundary. With this configuration, a substantially linear average light intensity can be achieved across frames, thereby reducing or eliminating display distortion that is often present in other PWM cycle synchronization techniques.

Abstract: A communications device comprises a receiver for receiving an input signal operably coupled to analogue to digital converter logic. The analogue to digital converter logic is operably coupled to control logic via a signal analyser arranged to analyse a converted received input signal, output from the analogue to digital converter logic to determine at least one characteristic of the received signal. The control logic is arranged to vary a dynamic range of the analogue to digital converter logic depending on the at least one determined characteristic of the received input signal.

Abstract: A memory has first and second memory arrays and first and second sense amplifiers coupled to the first and second memory arrays, respectively. A verify data line is coupled to first outputs of the first sense amplifier and the second sense amplifier as well as to a program/erase controller. The verify data line has a first logic circuit having a first input coupled to the first output of the first sense amplifier and an output. A second logic circuit has a first input coupled to the output of the first logic circuit, a second input coupled to the first output of the second sense amplifier, and an output. A global data line is coupled to a second output of the first sense amplifier and a second output of the second sense amplifier. A global sense amplifier is coupled to the global data line.

Abstract: A fast motion estimation system that determines a reference macroblock or sub-block combination within a reference frame for a current macroblock in a current frame includes a memory, a reference macroblock search circuit, a sub-block combination search circuit, and a comparator circuit. The reference macroblock search circuit determines a motion vector, multiple difference values, and a cost value for each macroblock within the reference frame according to a fast motion estimation search pattern, and stores the motion vector and the difference values in the memory. The sub-block combination search circuit searches the motion vector and the difference values in the memory for determining a corresponding one of multiple lowest cost sub-block combinations for each of multiple sub-block motion modes. The comparator circuit determines a lowest cost macroblock and selects from among the lowest cost macroblock and the lowest cost sub-block combinations to determine the reference macroblock.

Abstract: A method of forming a portion (10) of a compound semiconductor MOSFET structure comprises forming a compound semiconductor layer structure (14) and an oxide layer (20) overlying the same. Forming the compound semiconductor structure (14) includes forming at least one channel material (16) and a group-III rich surface termination layer (18) overlying the at least one channel material. Forming the oxide layer (20) includes forming the oxide layer to overlie the group-III rich surface termination layer and comprises one of (a) depositing essentially congruently evaporating oxide of at least one of (a(i)) a ternary oxide and (a(ii)) an oxide more complex than a ternary oxide and (b) depositing oxide molecules, with use of at least one of (b(i)) a ternary oxide and (b(ii)) an oxide more complex than a ternary oxide.

Abstract: Methods (1500) and corresponding systems (400, 500) for determining and correcting a DC offset in a receiver operate to sample (1503) a signal to provide complex samples; estimate (1505) a Direct Current (DC) offset corresponding to each of the complex samples, the estimating the DC offset further including solving a plurality of equations relating to the plurality of complex samples, e.g., N simultaneous equations in N samples with a power of the signal invariant across the N samples, to deterministically derive offset values; and then remove (1517) the DC offset from the signal.

Abstract: Embodiments of the present invention provide a method of forming gate stacks for field-effect-transistors.

Abstract: An apparatus (200) and method (300) for receiving a communications signal. A spread spectrum signal demodulator (210) is adapted to demodulate a packet header (110) of a data packet (102) that is communicated by a wireless communications signal. The packet header (110) is modulated with a spread spectrum technique and the spread spectrum signal demodulator (210) produces a packet header detection signal (220) representing a successful detection of a predefined packet header value. A non-spread spectrum signal demodulator (212) is communicatively coupled to the spread spectrum signal demodulator (210) and demodulates, in response to the packet header detection signal (220), a non-spread spectrum modulated data payload within the data packet. A data output select (234) produces demodulated data produced by either one or both the spread spectrum signal demodulator (210) and the non-spread spectrum signal demodulator (212).

Abstract: A pulse width modulation (PWM) wave output circuit that efficiently and accurately outputs dual PWM waves includes two comparators, an OR circuit, and an AND circuit. A voltage generator supplies the comparators with ramp voltages having the same wave height and shifted phases. The comparator compares the ramp voltages with the reference voltage and provides the comparison results to the OR circuit and the AND circuit. The OR circuit outputs a first modulation wave, and the AND circuit generates a second modulation wave. Accordingly, modulation waves having different duties are output based on ramp voltage having different phases.

Abstract: Methods (400, 500) and corresponding systems (100, 200, 300) for managing a packet (318) for transmission include obtaining a quality of service (QoS) parameter value for a data stream (404), and determining one or more QoS statistics for previously transmitted data (406). Thereafter, a packet is selected from the data stream (408), and scheduling information is estimated for the packet (410) based upon the QoS statistics and the QoS parameter value. The scheduling information is assigned (414) to the packet. A transmission time window of a transmission buffer is determined (506). If the scheduling information assigned to the packet falls within the transmission time window (508), the packet is queued for transmission in the transmission buffer. The labeled packet can be arranged among one or more queued packets in response to comparing scheduling information of the labeled packet and the queued packets.

Abstract: Aqueous liquid cleaning composition for wet cleaning of the sidewalls and bottom of vias formed in a dielectric layer of a semiconductor device, said composition comprising: c) hydrofluoric acid; d) a corrosion inhibitor which is a polyazo corrosion inhibitor or carboxylic acid corrosion inhibitor.

Abstract: A method includes providing a debug instruction and providing a debug control register field, where if the debug control register field has a first value, the debug instruction executes a debug operation and where if the debug control register field has a second value, the debug instruction is to be executed as a no-operation (NOP) instruction. A data processing system includes instruction fetch circuitry for receiving a debug instruction, a debug control register field, and debug execution control circuitry for controlling execution of the debug instruction in a first manner if the debug control register field has a first value and in a second manner if the debug control register field has a second value, where in the first manner a debug operation is performed and in the second manner no debug operation is performed.