Patents Assigned to Freescale
  • Method and device for high speed testing of an integrated circuit
    Patent number: 7689897
    Abstract: An integrated circuit and a method for testing an integrated circuit.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Eyal Salomon, Amir Zatlzman
  • Integrated circuit memory having dynamically adjustable read margin and method therefor
    Patent number: 7688656
    Abstract: A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, including a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shayan Zhang, Hema Ramamurthy, Zheng Xu, Michael D. Snyder
  • Transistor with differently doped strained current electrode region
    Patent number: 7687337
    Abstract: A transistor is formed by providing a semiconductor layer and forming a control electrode overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess and a second recess on opposing sides of the control electrode. A first stressor is formed within the first recess and has a first doping profile. A second stressor is formed within the second recess and has the first doping profile. A third stressor is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Mark C. Foisy
  • Current driver suitable for use in a shared bus environment
    Patent number: 7688113
    Abstract: A transceiver suitable for interfacing a logic device to a shared bus includes a transmit node that receives an input signal from the logic device and an I/O node, that is coupled to the shared bus. The transceiver may be designed for use with a shared-bus, single master, multiple slave architecture, e.g., a Local Interconnect Network (LIN). In a LIN compliant implementation, the transceiver may be suitable for use in at least some types of automobiles and other motorized vehicles. Control logic coupled to the transmit node may assert a current driver enable signal in response to detecting an assertion of the input signal. A current driver of the transceiver is configured to draw a time varying driver current from the shared bus node after detecting an assertion of the current driver enable signal. The driver current may cause a sinusoidal transition of the shared bus voltage.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ivan Carlos Ribeiro Nascimento, Walter Luis L. Tercariol
  • Method of forming a semiconductor isolation trench
    Patent number: 7687370
    Abstract: A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Toni D. Van Gompel, John J. Hackenberg, Rode R. Mora, Suresh Venkatesan
  • Integrated circuit and a method for measuring a quiescent current of a module
    Patent number: 7688100
    Abstract: A method for evaluating a quiescent current, the method includes: measuring, when a module is at a first mode, a first voltage drop on a first resistor that is coupled between a supply pin of an integrated circuit that comprises the module and a first test pin of the integrated circuit; assessing, when the module is at a second mode, a second voltage drop on a second resistor that is coupled between the supply pin and a second test pin of the integrated circuit; and evaluating a quiescent current of the module in response to the first and second voltage drops; wherein expected values of quiescent current of the module differ from one mode to the other; and wherein a resistance of the first resistor differs from the resistance of the second resistor.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Dan Kuzmin, Michael Simkhis
  • Controller and method for controlling an ignition coil
    Patent number: 7686000
    Abstract: A controller for an ignition coil, the controller comprising means for determining a rate of change of current flow through a primary winding of the ignition coil; and means for switching off current flow through the primary winding of the ignition coil as a function of the rate of change of current.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Michael R. Garrard
  • Fabrication of a semiconductor device with stressor
    Patent number: 7687354
    Abstract: In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Stefan Zollner
  • Self-aligning resonator filter circuits
    Patent number: 7689193
    Abstract: An embodiment of a self-aligning resonator filter circuit includes a tunable resonator having a filter output node, an oscillator having an oscillator output node, a resistance element connected between the oscillator output node and the filter output node when the self-aligning resonator filter circuit is in a tuning mode, and a phase detector loop controller coupled between the oscillator output node and the filter output node. The phase detector loop controller is configured to measure a phase difference across the resistance element, and to adjust the tunable resonator in response to the phase difference.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David P. Lester, Allan P. Chin, Luciano Zoso
  • Design rule checking system and method, for checking compliance of an integrated circuit design with a plurality of design rules
    Patent number: 7689951
    Abstract: In a design rule checking system for checking whether or not an integrated circuit design complies with design rules specifying limit values for respective geometric parameters, non-binary functions are used to model the way in which systematic yield loss varies with the value of the geometric parameters. This enables a value to be assigned to systematic yield loss in cases where the geometric parameter is compliant with the design rule but takes a value close to the design rule limit.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Lionel Riviere Cazeaux
  • Method for generating a output clock signal having a output cycle and a device having a clock signal generating capabilities
    Patent number: 7688127
    Abstract: A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Lavi Koch, Anton Rozen
  • METHOD FOR TESTING A VARIABLE DIGITAL DELAY LINE AND A DEVICE HAVING VARIABLE DIGITAL DELAY LINE TESTING CAPABILITIES
    Publication number: 20100072979
    Abstract: A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.
    Type: Application
    Filed: January 5, 2007
    Publication date: March 25, 2010
    Applicant: Freescale Semiconductor,Inc
    Inventors: Yefim-Haim Fefer, Mikhail Bourgart, Segey Sofer, Yoav Weizman
  • METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT
    Publication number: 20100077364
    Abstract: Method and apparatus for designing an integrated circuit, IC, layout by identifying one or more defects in a feature within the IC layout. Determining if an identified defect is improvable. Calculating an improvability metric of the IC layout based on the number of improvable defects and the total number of identified defects.
    Type: Application
    Filed: January 5, 2007
    Publication date: March 25, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Lionel J. Riviere-Cazeaux, Ashish Rajput
  • Integrated circuit including clip
    Patent number: 7683465
    Abstract: A semiconductor device is provided that includes a leadframe, a die, and a clip. The leadframe has a flag and a power pad. The die is coupled to the flag. The clip comprises a die retaining section and a pad section. The die is coupled to the die retaining section, and the pad section extends from the die retaining section. The pad section is coupled to the power pad.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vasile Romega Thompson, Zhi-Gang Bai
  • Balun transformer with improved harmonic suppression
    Patent number: 7683733
    Abstract: An electronic assembly includes a substrate (66), a balun transformer (42) formed on the substrate (66) and including a first winding (50) and a second winding (52), each having respective first and second ends, and a reaction circuit component (48) formed on the substrate (66) and electrically coupled to the second winding (52) between the first and second ends thereof. The balun transformer (42) and the reaction circuit component (48) jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component (48) is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Qiang Li, Jonathan K. Abrokwah, Olin L. Hartin, Lianjun Liu
  • Logic threshold acquisition circuits and methods using reversed peak detectors
    Patent number: 7684518
    Abstract: A circuit is provided which generates a first output signal and a second output signal. The circuit includes a reference signal input having a reference value, a first positioning circuit, and a second positioning circuit. The first positioning circuit generates the first output signal responsive to a first differential input signal and the reference signal, and the second positioning circuit generates the second output signal responsive to a second differential input signal and the reference signal. In one implementation, the positioning circuits may be reversed peak detectors. A minimum value of the first output signal and a minimum value of the second output signal are positioned along a common axis at values greater than or equal to the reference value.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dejan Mijuskovic, Frederick H. James
  • System and method for handling asynchronous data in a wireless network
    Patent number: 7684380
    Abstract: A method is provided for transmitting wireless signals in a network comprising a network coordinator and one or more remote devices. The available transmission time is divided into a plurality of superframes, each of which is further divided up into a beacon duration, one or more management time slots, one or more guaranteed time slots, and one or more asynchronous time slots. Each of the management time slots, guaranteed time slots, and asynchronous time slots are assigned to one of the one or more remote devices. The network coordinator sends a beacon to the one or more remote devices during the beacon duration. The device or coordinator assigned to the current guaranteed time slot sends frames of isochronous data in the current guaranteed time slot. The device or coordinator assigned to the current asynchronous time slot sends frames of asynchronous data in the current asynchronous time slot.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Knut T. Odman
  • Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array
    Patent number: 7684264
    Abstract: A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bradford L. Hunter, James D. Burnett, Andrew C. Russell, Shayan Zhang
  • III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same
    Patent number: 7682912
    Abstract: A method of forming a III-V compound semiconductor structure (10) comprises providing a III-V compound semiconductor substrate including a semi-insulating substrate (12) having at least one epitaxial layer formed thereon and further having a gate insulator (14) overlying the at least one epitaxial layer. The at least one epitaxial layer formed on the semi-insulating substrate comprises an epi-structure suitable for use in the formation of a channel of a III-V compound semiconductor MOSFET device, wherein the channel (30) having a first polarity. The method further comprises forming a charge layer (22) at a surface of the gate insulator, the charge layer having a second polarity, wherein the second polarity is opposite to the first polarity.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Matthias Passlack, Ravindranath Droopad, Karthik Rajagopalan
  • System and method for reducing edge effect
    Patent number: 7684504
    Abstract: A channel estimator (150) is provided that comprises: an extension circuit (410) configured to receive a pilot signal (510), and add front and back extension signals (620, 630) to a front and back of the pilot signal, respectively, creating a first signal (610), the front and back extension signals being extension of a first and last symbol, respectively, in the pilot signal; an IDFT circuit (420) configured to perform an IDFT function on the first signal, generating a second signal (710); a signal processing element (430, 440, 470, 480) configured to perform one or more operations on the second signal, generating a third signal (910); a DFT circuit (450) configured to perform a DFT function on the third signal, generating a fourth signal (1010); and a reduction circuit configured to cut off front and back ends of the fourth signal, generating a channel estimation signal (1110).
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: March 23, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Ahsan U. Aziz