Abstract: A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material (320), thereby forming a trench isolation structure. A channel region (326) is defined in the semiconductor layer adjacent to the trench isolation structure.

Abstract: A method of determining a synchronous phase includes receiving a correlation sequence, and selecting one or more correlated signals from the correlation sequence. Then, when the number of selected correlated signals is odd, the synchronous phase corresponding to a central correlated signal is selected.

Abstract: A method for making a one time programmable (OTP) memory array includes providing a wafer comprising a buried insulator layer and a semiconductor layer over the buried insulator layer and forming a plurality of bit lines in the semiconductor layer. Each of the plurality of bit lines comprise a portion of the semiconductor layer and the plurality of bit lines are separated from each other by isolation regions formed in the semiconductor layer. The method further includes forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions, and forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer.

Abstract: A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting.

Abstract: A method of continuous testing of repetitive functional blocks provided on an integrated circuit (IC) which includes selecting one of the repetitive functional blocks at a time for testing, substituting a test repetitive functional block for a selected repetitive functional block, and testing the selected repetitive functional block during normal functional mode of the IC. An IC which includes repetitive functional blocks for performing corresponding functional block operations during normal functional mode of the IC, and a test system which performs continuous testing of each repetitive functional block while the functional block operations are performed during normal functional mode of the IC. One block may be tested during normal operation for each IC reset event without transferring or copying state information. Multiple blocks may be tested one at a time during normal operation by transferring state information between a selected block and a test block.

Abstract: A method that locates a plurality of die for forming a plurality of packaged integrated circuits. A frame is placed over the support structure, wherein the frame includes a plurality of openings therein and each opening of the plurality of openings has at least two walls. Each die of a plurality of die is placed over the support structure, wherein each die has at least two adjacent edges. The relative placing of the frame and the die results in each die being in an opening of the plurality of openings. Encapsulant is applied to the plurality of die. Either or both of the plurality of die and frame are moved in relation to the other in a manner that causes the two adjacent edges of each die of the plurality of die to substantially abut to and align with the two walls of an opening of the plurality of openings.

Abstract: An integrated passive device (20) includes a first wafer (22), a first integrated device (28) formed on a first surface (24) of the wafer (22), and a second integrated device (30) formed on a second surface (26) of the wafer (22), the second surface (26) opposing the first surface (24). A microelectromechanical (MEMS) device (72) includes a second wafer (74) having a MEMS component (76) formed thereon. The integrated passive device (20) and the MEMS device (72) are coupled to form an IPD/MEMS stacked device (70) in accordance with a fabrication process (90). The fabrication process (90) calls for forming (94) the second integrated device (30) on the second surface (26) of the wafer (22), constructing (100) the MEMS component (76) on the wafer (74), coupling (104) the wafers (22, 74), then creating the first integrated device (28) on the first surface (24) of the first wafer (22).

Abstract: A pressure sensor includes a first set of electrodes, a second set of electrodes, and a common electrode. The first and second sets of electrodes overlie an insulative surface, wherein the first set of electrodes represent sense capacitor bottom electrodes and the second set of electrodes represent reference capacitor bottom electrodes. The second set of electrodes is configured in an interleaved arrangement with the first set of electrodes, wherein the geometry of individual electrodes of the first set of electrodes substantially matches the geometry of individual electrodes of the second set of electrodes.

Abstract: A method of acquiring, at a receiver, fine timing synchronization for an Orthogonal Frequency Division Multiplexing (OFDM) signal as transported over a channel, includes determining an impulse response of the channel; dynamically creating a window function corresponding to the impulse response; and selecting a multiplicity of samples of the OFDM signal in accordance with the window function, where the multiplicity of samples are time aligned with an OFDM demodulator. A corresponding synchronizer includes a correlator for cross correlating a received preamble with a known preamble to provide an impulse response corresponding to the channel; a window generator configured to dynamically create a window function corresponding to the impulse response; and a selector configured to select a multiplicity of samples of the OFDM signal in accordance with the window function, where the multiplicity of samples are time aligned with a Fast Fourier Transform window associated with an OFDM demodulator.

Abstract: An AM receiver including an AM demodulator for demodulating an AM signal received by an antenna coupled to the AM demodulator is provided. The AM receiver further includes a bandpass filter for receiving the demodulated signal and generating a bandpass filtered signal. The AM receiver further includes a moving average filter for receiving the bandpass filtered signal and generating a moving averaged signal and a highpass filter for receiving the moving averaged signal and generating a highpass filtered signal. The AM receiver further includes an averaging filter for receiving the highpass filtered signal and generating an averaged signal and a summer for receiving the averaged signal and the highpass filtered signal and generating a difference signal. The AM receiver further includes a comparator for generating a noise blanking signal based on a comparison of the difference signal with a threshold.

Abstract: A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.

Abstract: A treatment solution for a semiconductor wafer comprising water, a passivating reagent and a surfactant. The treatment solution is either mixed with a cleaning fluid, a rinsing fluid or a drying vapor, and is used in a cleaning apparatus employing a Marangoni dryer.

Abstract: Techniques for testing a semiconductor wafer are disclosed. One technique includes measuring a parameter for each of the semiconductor dies in a region of the wafer and determining an adaptive threshold for the region based on the measured parameters. The parameter measured for each die in the region is then compared to the adaptive threshold to determine a qualification status for each die. Accordingly, the semiconductor dies of the wafer are qualified based on an adaptive threshold that varies according to the wafer region under test. This allows for detection of dies whose parameters vary significantly from other dies in a region, providing for detection of potentially faulty dies whose parameter measurements otherwise meet a fixed threshold set for the entire wafer, such as a Single Threshold Test Limit (STL) expectation for the wafer.

Abstract: A baseband receiver and corresponding methods are arranged and configured to mitigate effects of direct current (DC) distortion and process an Orthogonal Frequency Division Multiplexing (OFDM) signal as provided from a direct conversion radio or receiver. The baseband receiver includes an OFDM demodulator configured to demodulate the OFDM signal, a post processor coupled to the OFDM demodulator and configured to provide symbols corresponding to the OFDM signal, and a compensator coupled to at least one of the OFDM demodulator and the post processor and configured to reduce error rates out of the baseband receiver that result from DC distortion in the direct conversion radio.

Abstract: A memory system including a first memory for storing data and an ECC unit for accessing the first memory and for detecting errors in data retrieved from the first memory, and characterised by an error further processing arrangement operable to process errors detected by the ECC unit, the error further processing arrangement including a second memory for recording information relating to the detected errors. Also described is a method of operation in the memory system.

Abstract: A system (50) for cooling a target element (56) includes a structure (52) having an opening (62) extending through the layer (52), a pumping device (32) positioned behind the structure (52), and a target element (56) positioned in front of the structure (52). Transducers (58, 60) are positioned at opposing ends (74, 76) of the opening (62) between the structure (52) and the target element (56). The pumping device (32) drives a jet (70) of coolant through the opening (62) toward the target element (56). The transducers (58, 60) produce output signals (84, 86) that perturb the jet (70) to control oscillation of the jet (70) in order to stabilize the jet (70) for impingement with a predetermined location (96) on the target element (56). The jet (70) uniformly spreads from the location (96) to provide cooling over a surface (100) of the target element (56).

Abstract: A device for minimizing group delay mismatch in a quadrature receiver (402) having an in-phase channel and a quadrature-phase channel. The device includes a microprocessor (465) for determining an I/Q phase imbalance between digital signals on an in-phase channel and digital signals on a quadrature-phase channel, and for calculating a group delay mismatch between the in-phase channel and the quadrature-phase channel, and a group delay equalizer (426). The group delay equalizer includes a delay line (505 and 605) for delaying one of the in-phase channel and the quadrature-phase channel by one of a plurality of delays, based on an amount of group delay mismatch.

Abstract: A distributed processor-based system comprises a plurality of communicating platforms, wherein a number of platforms in the distributed processor-based system comprise at least one compiler, the at least one compiler being operably coupled to data type translation logic and arranged to generate a memory layout for the respective platform. In response to an indication for a communication to occur between a first platform and a second platform the data type translation logic translates a memory layout using data type attributes for data to be transferred from the first platform to the second platform based on at least one platform-specific characteristic, such that the data does not require translating when received at the second platform.

Abstract: A data processing control unit for controlling two or more data processing operations SMI1,SMI2. The data processing control unit may include a control memory in control data may be stored which represents information about access to a main memory by the two or more data processing operations. A control data controller may be connected to the control memory. The control data controller may include a control data controller input or receiving an access request from one or more of the data processing operations. The control data controller may modify the data in the control memory upon receiving the access request. A process controller may be connected to the control memory. The process controller may control at least a part of the data processing operations SMI1.SMI2 based on a comparison of data in the control memory with a criterion.

Abstract: A method of delineation of a packet-based data stream in order to identify a boundary between neighbouring packets in the data stream, wherein the data stream comprises a predetermined number of bits (N); the method comprising the steps of: processing the data stream to search for the boundary between neighbouring packets in the data stream; characterised in that the method further comprises calculating the greatest common divisor (GCD) of a bit skip integer (n) where (N) and (n) are co-primes; iteratively checking after each n bits to identify the boundary between the neighbouring packets.