Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.

Abstract: A method of conducting timing analysis on an integrated circuit design includes performing a first routing operation on the design to generate a first routed design that includes redundant vias, and storing the first routed design in a first design database, and performing a second routing operation on the synthesized design to generate a second routed design that does not include redundant vias, and storing the second routed design in a second design database. Then, extractions are performed on the first and second designs and delay calculations are performing on the first and second extractions files. The first and second delay calculations are compared to determine a delay difference between the first and second designs and timing analysis is performed using the delay difference.

Abstract: A method for generating a clock signal and a device having clock generating capabilities, the device includes: (i) a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; (ii) a second divider, adapted to receive an input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; (iii) a reconstruction circuit, connected to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and (iv) a selection circuit, connected to the first divider, second divider and reconstruction circuit, adapted to output an outp

Abstract: A method for reducing line edge roughness (LER) in a layer of photoresist is provided. In accordance with the method, a layer of photoresist is applied to a substrate. The layer of photoresist is then patterned and annealed in an atmosphere comprising at least one gas selected from the group consisting of hydrogen, nitrogen and fluorine-containing materials. Preferably, the anneal is performed after patterning the photoresist, but either immediately after, or subsequent to, the trim.

Abstract: A circuit comprises first, second, third, and fourth transistors. The first transistor has a first current electrode, a control electrode for receiving an input signal, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor for providing an output signal, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to a first power supply voltage terminal. The third transistor has a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to the first current electrode of the first transistor. The fourth transistor has a first current electrode coupled to the control electrode of the third transistor, a control electrode coupled to the control electrodes of the first and second transistors, and a second current electrode coupled to the control electrode of the first transistor.

Abstract: A multipath wideband communications receiver (100) having a plurality of RF signal paths (116, 136) covering different but overlapping frequency bands and a plurality of baseband signal paths (140, 150, 160, 170, 180, 190), the paths being re-configurable for sharing of the first and second paths in different ways in order to facilitate processing of received signals in different modes. Also, a rake receiver (800) employs a sigma-delta modulator arrangement (810) and programmable delays to provide fine delay adjustment. The sigma-delta modulator (810) may use sigma-delta circuitry from a sigma-delta A/D converters in a baseband paths of the receiver (100), that this may be achieved with no loss of functionality if in a particular reception configuration that sigma-delta A/D converter is not being utilized.

Abstract: Apparatus and methods are provided for overload recovery in high order sigma-delta feedback topologies. An apparatus is provided for an analog-to-digital converter. The analog-to-digital converter comprises a first integrator having a first input, wherein the first integrator is configured to produce a first integrated output. A first switched resistance element is coupled between the first input and the first integrated output, wherein the first integrated output is altered when the first switched resistance element is activated. A quantizer is coupled to the first integrated output, the quantizer having a digital output wherein the quantizer converts the first integrated output to a digital value. A digital-to-analog converter is coupled between the digital output and the first input, wherein the digital-to-analog converter converts the digital value to an analog value.

Abstract: A method of scheduling wireless communication for one or more data flows, wherein, for each data flow, there is: a corresponding queue to store data of that data flow; one or more quality-of-service parameters associated with that data flow; and a flow type associated with that data flow, there being a plurality of possible flow types; wherein the method comprises, during each time frame of a sequence of time frames, the steps of: maintaining, for each of the plurality of possible flow types, a queue list that identifies the queues corresponding to data flows of that flow type; and processing the queue lists in a predetermined order, in which processing a queue list comprises, for each queue identified in that queue list, attempting to schedule the communication of data stored on that queue during a current time frame in dependence upon the one or more quality-of-service parameters associated with the corresponding data flow and an amount of bandwidth available for the wireless communication during the curren

Abstract: A communication device is capable of supporting communication compliant with a Dual-Mode 2.5G and 3G interface baseband-radio frequency interface standard and comprises a data interface operably coupled to a number sub-systems and a clock circuit generating a plurality of clock phases for supporting communication there between. At least one of the number of sub-systems comprises a line driver and a line receiver; wherein the communication device is characterised in that the line receiver determines an end of a received data frame sent across the data interface and in response thereto switches itself off.

Abstract: A device (12) may have a pressure sensitive portion (17) which is protected from corrosion by a pressure transmitting material (20). Pressure transmitting material (20) may also be used to transmit pressure to pressure sensitive portion (17). A masking material (22) may be used to define an opening (26) in encapsulating material (24).

Abstract: A method (1000) for sharing charge between IO circuits, the method (1000) includes providing (1010) an integrated circuit that comprises multiple IO circuits, each comprising an IO pad. The method (1000) is characterized by including: determining (1020) to share a charge between multiple IO circuits; and sharing charge (1030) between the multiple IO circuits by coupling the multiple IO circuits to a shared circuit that is characterized by a state that reflects multiple iterations of sharing charge operations.

Abstract: An error correction apparatus comprises an input for receiving data. The received data includes error-check data. The apparatus also includes a processing resource arranged to calculate parity check data. A data store is coupled to the processing resource for storing look-up data for identifying, when in use, a location of an error in the received data. The look-up data is a compressed form of indexed error location data.

Abstract: A semiconductor wafer critical dimension measurement method comprising receiving an image of a site of the semiconductor wafer comprising a plurality of features, processing the image to measure at least one critical dimension of at least some of the features, analysing the critical dimension of each feature and determining the feature to be a non-defective feature or a defective feature, and using the critical dimension of at least some of any non-defective features as a measure of the critical dimension of features of the semiconductor wafer.

Abstract: A detector circuit for detecting the presence of a remote capacitive sensor having at least two terminals connected via a protection circuit that includes one or more capacitors, the detector circuit comprising: a current supply for changing the charge on the sensor and the protection circuit, a detector for measuring the voltage on one or more of the terminals; wherein the presence of the sensor is determined by changing the charge on the capacitive sensor and the one or more capacitors of the protection circuit in a predetermined manner such that the voltage measurement on the one or more terminals when the sensor is present is significantly different than when the sensor is absent.

Abstract: A system and method is provided for bit eye center retraining. In general, the system samples an incoming data stream to determine where transitions in the data stream occur, selectively compares the location of the transitions to the expected locations to produce difference values, and combines pairs of difference values to determine when the sample point of the data stream needs to be adjusted.

Abstract: An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance.

Abstract: In one form a memory and method thereof has a memory array having a plurality of memory cells. A bit line precharge operation is based on a clock edge of an external clock signal. A word line is selected after the beginning of the precharge operation. A sense operation is begun after enabling the word line, where the sense operation is for sensing a logic state of a memory cell. A data bit is output from the memory array corresponding to the sensed logic state of the memory cell. In one form the bit line precharge operation further comprises the bit line precharge operation having a predetermined duration that is independent of the clock signal, and the sense operation begins a predetermined delay time after enabling the word line, the sense operation having a variable duration.

Abstract: A system is described for generating a discrete noise-shaped variable switching frequency signal that may be used to define a digital pulse width modulation (“PWM”) period. The system may define a switching frequency waveform that may be used to generate a current switching frequency signal as a function of a system clock. The system may quantize the current switching frequency signal to generate a discrete switching frequency signal that is realizable with the system clock. The system may detect quantization noise and input the noise into the current switching frequency signal to eliminate or reduce discrete tones at the switching frequencies of a PWM signal spectrum.

Abstract: A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.

Abstract: In an integrated circuit having a plurality of modules and/or submodules that each performs a substantially same function, defective modules and/or submodules are determined by creating a test signature from an input test pattern. The output of each module and/or submodule is compared with the test signature and defective modules to identify defective modules and/or submodules. The identity of defective modules/submodules is stored on the integrated circuit for subsequent use by a customer. Integrated circuits having one or more defective modules/submodules are sold to customers with full disclosure of which modules/submodules are defective, thereby improving the yield associated with the product. Pricing of the product is discounted for products with less than full functionality.