Abstract: An apparatus (100, 200) and method (300) for sensing acceleration are provided. The method includes producing (305) a first signal in response to an acceleration sensed by a transducer, producing (310) a second signal based on the first signal, and actuating (315) the transducer in response to the second signal to remove offset in the transducer. The first signal represents the acceleration, and the second signal represents a low frequency component associated with an offset in the transducer. The apparatus (100) includes a transducer (102) producing a capacitance in response to the acceleration, a sensing system (104, 106, 108) producing a first signal from the capacitance representing the acceleration, and a compensation system (112, 110) coupled between the sensing system and transducer. The compensation system produces a second signal based on the first signal for substantially removing an offset of the transducer.

Abstract: A lock loop circuit (216) includes a precharge circuit (304), an oscillator circuit (306), and a calibration circuit (309). The calibration circuit includes at least one register (362). The precharge circuit provides a precharge signal (347). The oscillator circuit provides an output frequency signal (228) in response to a steering signal (334) that is based on the precharge signal. The calibration circuit, prior to the lock loop circuit entering a disabled mode of operation, determines a calibration value (368) for the precharge circuit based on the precharge signal and the steering signal. The calibration circuit stores the calibration value as a digital calibration value (370) in the register.

Abstract: A method is provided for constructing a microelectronic assembly. A semiconductor substrate having a MEMS device formed on a first portion thereof, a semiconductor device formed on a second portion thereof, and a build up layer having a first portion formed over the MEMS device and a second portion formed over the semiconductor device is provided. The first portion of the build up layer over the MEMS device is removed. A release body is formed adjacent to the MEMS device. A structural material is formed over the release body. An opening is formed in the structural material to expose the release body. The release body is removed through the opening to form a cavity between the MEMS device and the structural material. The opening in the structural material is sealed with a sealing material.

Abstract: Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

Abstract: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer (12) having first and second inputs and an output and at least one N-type isolation transistor (13, 19) having a source coupled to one or both of the second input and the output. The first input receives the data signal, the second input receives a supply potential, and the output couples to the low voltage logic device. The isolation transistor has a drain for receiving a first potential and is configured to supply a second potential to the output buffer when the gate receives a bias potential. The second potential based on the first potential. The bias potential is greater than the supply potential.

Abstract: Power switching apparatus comprising switch means having a control terminal and output terminals for connection in series between a power supply and a load. The switch means is responsive to a control signal applied to the control terminal to switch between an ON-state in which it supplies power supply current from the power supply through the output terminals to the load and an OFF-state in which it interrupts the supply of power through the output terminals to the load.

Abstract: An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source.

Abstract: A method and data processing system for accessing an entry in a memory array is provided using base and offset addresses without adding the base and offset addresses. PGZO encoding is performed on the address bits of the operands. The PGZO values are evaluated using wordline generators resulting in a plurality of possible memory array entry addresses. In parallel with the PGZO operations, a carry value is generated using other bits in the operands. The result of the carry operation determines which of the possible memory array entries is selected from the memory array.

Abstract: A trimming circuit and an electronic circuit that decreases the resistance of an activated transistor while reducing the number of resistors. The trimming circuit includes a plurality of series-connected units. Units for respectively changing adjusting resistances of Runit/2, Runit/4, Runit/8, and Runit/16 are each formed by a transistor, a series-connected resistor circuit, which has resistance Rt and which is connected in series to the transistor, and a parallel-connected resistor circuit, which has resistance Rm and which is connected to the transistor and the series-connected resistor circuit. The resistances Rm and Rt are determined in each unit such that the difference between the resistance Rm when the transistor is off and the resistance of the entire unit when the transistor is on determines the adjusting resistance.

Abstract: A apparatus (700) and method (600) are presented for preventing glitches and data loss in an Digital Base Band (DBB) portion (110) of an Ultra Wideband (UWB) receiver. a first and a second recovered clock (111, 112) and an external clock (109) can be input to a switch (116). Logical rules (490) can be used to determine conditions under which to hold the state of an output clock (310, 320) based on the states of a first clock (410, 420, 430, 440) and a second clock (450, 460, 470, 480) and the state of a switch request signal (312). In addition to holding the state of the output clock, a first data stream (501) associated with the first clock and a second data stream (502) associated with the second clock can be synchronized such that when switching from the first to the second clock no data loss will be experienced in the data stream.

Abstract: A device 20 includes substrates 22 and 24 coupled to form a volume 32 between the substrates. A surface 28 of the substrate 22 faces a surface 30 of the substrate 24. A metal-insulator-metal capacitor 34 is formed on one of the surfaces 28 and 30. A conductive element 58 spans between a top electrode 56 of the capacitor 34 and the other surface 28 and 30. Vias 64 and 66 extend through the substrate 22 and are electrically interconnected with the conductive element 58 and a bottom electrode 52 of the capacitor 34. Another device 72 includes an underpass transmission line 92 formed on a surface 80 of a substrate 74 within a volume 84 formed between the substrate 74 and another substrate 76. The line 92 underlies an integrated device 96 formed on a surface 78 of the substrate 74.

Abstract: A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.

Abstract: A device and a method for testing a DMA controller. The device includes: (i) a DMA controller that includes a first data transfer path and a second data transfer path, wherein the first data transfer path and the second data transfer path are mutually independent; (ii) a test unit, connected to the first and second data transfer paths, that is adapted to control a transfer of data between the first data transfer path and the second data transfer path during a test mode, while masking from a first memory unit coupled to the DMA controller, at least one control signal associated with the transfer of data.

Abstract: A method of transferring image data to a composite memory space comprises including masking data defining a reserved output area in a first memory space and containing first time-varying data having a first frame rate associated therewith. Second time-varying image data is stored in a second memory space and is associated with a second frame rate. At least part of the first image data is transferred to the composite memory space and at least part of the second image data is transferred to the composite memory. The mask data is used to provide the at least part of the second image data such that, when output, the at least part of the second image data occupies the reserved output area.

Abstract: A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronisation logic operably coupled to a counter, such that data is sampled by the timing synchronisation logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterised in that the timing synchronisation logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronisation.

Abstract: A regulator circuit for efficiently and accurately outputting a target voltage with a simple circuit configuration. The regulator circuit includes an output circuit, a comparator, a counter block, a latch block, and a decoder block. When the target voltage is applied to an output terminal of the output circuit, the output circuit supplies the comparator with feedback voltage. Further, the feedback signal is provided to the counter block. The counter block performs counting in correspondence with the feedback signal. The latch block holds the signal acquired from the counter block and provides the held signal to the decoder block. The decoder block supplies the comparator with reference voltage. The comparator compares the reference voltage and the feedback voltage and controls the counting.

Abstract: A semiconductor device is provided which comprises a semiconductor layer (109), a dielectric layer (111), first and second gate electrodes (129, 131) having first and second respective work functions associated therewith, and a layer of hafnium oxide (113) disposed between said dielectric layer and said first and second gate electrodes.

Abstract: A data communication network. The network includes a transmitter unit for transmitting data and a receiver unit for receiving data from the transmitter unit. The network has two or more data channels via which data may be transmitted by the transmitter unit to the receiver unit. The receiver unit includes a receiver channel selection unit for selecting a reception channel from the at least two data channels. The receiver channel selection unit operates independent from a selection of a transmission channel by a transmission channel selection unit in the transmitter unit. The transmission channel selection unit is arranged to select a transmission channel from the at least two data channels to transmit data to the receiver unit.

Abstract: Disclosed are example techniques for frame-based power management in a light emitting diode (LED) system having a plurality of LED strings. A voltage source provides an output voltage to drive the LED strings. An LED driver generates a frame timing reference representative of the frame rate or display timing of a series of image frames to be displayed via the LED system. An update reference is generated from the frame timing reference. The LED driver monitors one or more operating parameters of the LED system. In response to update triggers marked by the update reference, the LED driver adjusts the output voltage of the voltage source based on the status of each of the one or more monitored operating parameters (either from the previous update period or determined in response to the update trigger), thereby synchronizing the updating of the output voltage to the frame rate (or a virtual approximation of the frame rate) of the video being displayed.

Abstract: A method (32) of packaging integrated circuit (IC) dies (48) includes applying (36) a laminating material (44) to a wafer (40), and separating (46) the wafer (40) into multiple IC dies (48) such that the laminating material (44) is applied to back surfaces (52) of the IC dies (48). Each of the IC dies (48) is positioned (62) with an active surface (50) facing a support substrate (56). An encapsulant layer (72) is formed (64) overlying the laminating material (44) and the back surfaces (52) of the IC dies (48) from a molding compound (66). The molding compound (66) and the laminating material (44) are removed from the back surfaces (52) of the IC dies (48) to form (76) openings (78) exposing the back surfaces (52). Conductive material (84, 88) is placed in the openings (78) and functions as a heat sink and/or a ground for the IC dies (48).