Abstract: A transmitting device comprising a transmitter, an antenna and a tuning means comprising a matching network connectable between the transmitter and the antenna, the matching network comprising a plurality of capacitors; characterised in that the tuning means further comprises a means of selectively individually adjusting the capacitors to increase the output power of the transmitting device.

Abstract: A wireless communication unit comprises a frequency generation circuit employing a fractional-based synthesiser, a voltage controlled oscillator circuit and a charge pump. A characterising function characterises a charge pump gain at a number of synthesized frequencies. A memory element is arranged to store characterised parameters. A scaling function is operably coupled to the memory element and the voltage controlled oscillator circuit and arranged to compensate for Kv/N variation over a tuning line voltage applied to the voltage controlled oscillator circuit, at a synthesized frequency. In this manner, the bandwidth (open loop gain) of a Phase Locked Loop remains relatively constant, to ensure the phase noise and lock time performance of the transmitter is better than 50 ?sec and the Rx performance is better than 125 ?s. Advantageously, only one loop filter is required to cover both Rx and Tx modes of operation.

Abstract: An integrated circuit and a method for testing an integrated circuit.

Abstract: In the field of immersion lithography, it is known to provide a liquid between an optical exposure system and a wafer carrying layers of photosensitive material to be irradiated with a pattern by the optical exposure system. However, bubbles are known to form or exist in the liquid, sometimes close to a surface of the wafer resulting in scattering of light emitted from the optical exposure system. The scattering causes the pattern recorded in the layers of photosensitive material to be corrupted, resulting in defective wafers. Therefore, the present invention provides a bubble displacement apparatus comprising a drive signal generator for driving a force generator arranged to generate a force in response to a drive signal generated by the drive signal generator. The force generated urges the bubble away from the surface.

Abstract: First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor is permanently transferred to a channel of the second transistor. The stressor layer is removed except adjacent the gate electrode sidewalls of the first transistor and the second transistor where the stressor layer is used as gate sidewall spacers. Electrical contact to electrodes of the first transistor and the second transistor is made while using the gate sidewall spacers for determining a physical boundary of current electrodes of the first and second transistors. Subsequently formed first and a second stressors are positioned close to transistor channels of the first and second transistors.

Abstract: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.

Abstract: A polish pad (120) and platen (130) assembly for use in chemical mechanical polishing of semiconductor devices includes a platen (130) having a grooved or channeled surface (136) which is sealed from the processing environment by an ungrooved portion (131) at the periphery of the platen (130). In addition, the platen (130) includes one or more passageways (132) that provide a pathway to ambient or sub-ambient environment. The combination of the sealing region (131) and the passageway(s) (132) prevent liquids, vapors or other undesirable contaminants from infiltrating between the pad and platen, and also vent trapped air pockets between the pad and platen.

Abstract: A method is provided for making a silicided gate in a semiconductor device. In accordance with the method, a gate (213) is provided which comprises a first portion (214) and a second portion (213). The first portion of the gate has a width w1 and the second portion of the gate has a width w2 as taken along a plane perpendicular to the length of the gate, wherein w2>w1. A layer is silicide (231) is then formed on the second portion.

Abstract: An analog-to-digital converter (ADC) includes a multiplying digital-to-analog converter (MDAC) having a plurality of capacitors and a plurality of capacitor positions. The ADC generates a random number for a conversion cycle. The ADC configures each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the random number for the conversion cycle. The ADC converts, for the conversion cycle, a voltage of an analog signal to a digital value based on the capacitor configurations.

Abstract: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or a combination thereof.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first and second charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode is formed adjacent to the first sidewall. In another embodiment, third and fourth charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.

Abstract: A calibration device for a phase locked loop arranged to generate an output frequency based upon a first frequency range of an input signal applied to a first input and a second frequency range of the input signal applied to a second input, the calibration phase locked loop synthesizer device comprising an estimator arranged to use a two dimensional estimation algorithm with a signal value indicative of a mismatch between the first input path and the second input path to determine an estimate of the mismatch to allow matching of the first input path and the second input path.

Abstract: A method (500) and an apparatus (300) are presented for processing a signal in a receiver in accordance with Ultra Wideband (UWB) protocol. The received signal is acquired during a first preamble portion (411) of a data frame associated with the UWB protocol. During acquisition a first Automatic Gain Control (AGC) operation (606) is performed associated with a noise component of the signal. A second AGC operation (608) associated with a pulse component of the signal is performed after the acquiring the signal during a second preamble portion (413).

Abstract: An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.

Abstract: A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated.

Abstract: A switch arrangement for providing a drive signal at an output comprises a drive switch coupled to the output of the switch arrangement and a regulating element coupled in series between the drive switch and a power supply input of the switch arrangement. The drive switch is operable to provide the drive signal at the output. The switch arrangement is characterised in that the regulating element is coupled in a cascode arrangement with the drive switch such that in operation the regulating element limits the voltage drop across the drive switch to a predetermined level.

Abstract: A workpiece, including a substrate and overlying layer, can be exposed to a region, such as a process chamber, to test for the presence of an analyte. Detected fluorescence emission signals during TXRD due to the substrate are significantly reduced, allowing the analyte to be detected at lower concentrations. In one embodiment, the substrate can principally include silicon, and the layer can include an organic layer (e.g., resist, polyimide, etc.) The organic layer allows analytes with an atomic number as low as 11 to be detected. Also, the detection limits for nearly all analytes can be reduced because the detector is not receiving a disproportionately larger number of fluorescence emission from silicon. In additional, areal information regarding the analyte with respect to position over the substrate can be obtained. Detection levels as low as 1E9 atoms/cm2 are possible.

Abstract: An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming (405) a first die on a substrate, forming (410) a second die on the substrate, and forming (415) a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a PA (101), a second die having a capacitor (102), and a metal interconnect (108) coupled to the PA and the first capacitor. The metal interconnect (108) has an inductance. The capacitor (102) and metal interconnect (108) form a shunt impedance.

Abstract: A method of generating a layout of one or more planar double gate transistors can include generating a single gate transistor layout at least in part from one or more double gate transistor circuits, logic diagrams, or any combination thereof, and generating the planar double gate transistor layout at least in part from the single gate transistor layout. The method is highly flexible regarding the generation and adjusting of gate shapes and gate contact shapes to ensure the proper connection of the gates to voltage or signal lines, and when such generation, adjusting, or any combination thereof is performed. In one embodiment, a data processing system can include a program that has code in the form of instructions to carry out the method.