Abstract: A self-routing communication network (100) having: a plurality of nodes (N1-N15); a plurality of star couplers (S1-S4) each having a plurality of inputs and a plurality of outputs; and communication paths coupled between the plurality of star couplers and the plurality of nodes for communication therebetween of frames of information, including at least one redundant communication path (L1-L3), and each of the star couplers sensing which of its inputs first receives a frame and passing only the frame first received. The frames each have a fram-start-sequence (FSS), and the star couplers change the fram-start-sequences before outputting the frame of information e.g. by reducing the size of a frame's fram-start-sequence by a predetermined amount (e.g., 2 bits), whereby interconnection failure may be diagnosed by analyzing the frame-start-sequence.

Abstract: An integrated circuit (10) comprises a plurality of non-volatile memory cells (14) and a charge distribution ramp rate control circuit (11). Each memory cell of the array (12) includes a charge storage region and a plurality of terminals. The charge distribution ramp rate control circuit includes a capacitor (62,116,144) having a first plate electrode coupled to at least one terminal of the plurality of terminals, and a second plate electrode. The charge distribution ramp rate control circuit further includes a bandgap generated current source (58,106,136) for providing a reference current to determine a ramp rate of a voltage at the at least one terminal.

Abstract: An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a transition detector. The pull circuit causes the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory. The data out control circuit has an output terminal for providing the read command and a first predetermined number of address bits to the output terminal. The transition detector is coupled to an input terminal for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits. The transition detector will detect a transition of the input terminal when a correct number of address bits have been provided.

Abstract: An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells.

Abstract: A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.

Abstract: A method for testing a noise immunity characteristic of an analog circuit of an integrated circuit. The device includes: an analog circuit, an internal stable reference signal source, an internal power supply module connected to the analog circuit and adapted to receive, via first input, a high level voltage supply, the device is characterized by including: a signal modulator that is adapted to provide, during a test period, a noisy signal to a second input of the internal power supply module; whereas the internal power supply module is adapted to output a noisy power supply to the analog circuit, in response to the noisy signal; whereas device is adapted to output an output signal representative of a noise immunity characteristic of the analog circuit. The method includes: providing a high level supply voltage to a first input of an internal power supply module of an integrated circuit and receiving signals from the integrated circuit representative of the performance of the analog circuit.

Abstract: A wafer comprises a multi-layer structure. The multi-layer structure includes a first device structure neighbouring an area for receiving alignment markers. A plurality of alignment markers extend into the multi-layer structure and are located within the area for receiving alignment markers. The plurality of alignment markers is arranged to prevent propagation of a crack, when occurring, beyond a material-dependent critical length in a part of the multi-layer structure corresponding to the area for receiving the alignment structure. The material-dependent critical length is associated with the part of the multi-layer structure.

Abstract: A system and method for detecting flicker in a digital image. The system and method detects flicker by performing a frame-to-frame comparison of image data. The frame-to-frame comparison of image data is based on dividing each image into multiple columns, and performing a weighted sum of the pixel luminance in each column using a pattern of alternating sign weights. The weighted sum of luminance for each column in a first frame is compared to the weighted sum of luminance for that column in a second frame to determine if there is a simultaneous luminance variation in those columns. For example, if the difference between weighted sums of luminance between frames exceeds a threshold value in a predetermined number of columns then there is a simultaneous luminance variation in those columns, and a horizontal pattern of flicker has been detected in the image data.

Abstract: Different from conventional equalizers, the output of an SAIC (Single Antenna Interference Cancellation) linear equalizer in GSM/EDGE wireless communication systems is a real signal combined from two real FIR (Finite Impulse Response) filter outputs. Each of the FIRs separately uses the real and imaginary components of the ½ ? de-rotated received signal as input. The real-valued output of the SAIC equalizer creates difficulty to estimate and correct the frequency errors due to receiver LO and Doppler shift. Disclosed is an efficient and effective solution to the estimation and correction of the frequency error through an assistant signal generated by two additional FIR filters. The assistant signal and the SAIC equalizer output are used to estimate the frequency error, which is combined with the SAIC equalizer output and the assistant signal to give the frequency error corrected SAIC equalizer output.

Abstract: A modulus divider controller coupled to a modulus divider for generating a synthesized clock from a reference clock, wherein the modulus divider generates a divided clock, is provided. The modulus divider controller may further include a first binary stream switching circuit having a first output and a second output. The first binary stream switching circuit may further have a logic low input and a logic high input and a first switching input corresponding to a most significant bit of a count generated by a synchronous counter, wherein the synchronous counter counts the divided clock. The first binary stream switching circuit may further have a second switching input corresponding to a least significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock.

Abstract: A multi-mode transmitter architecture is configurable for multiple modulation modes using either polar or polar-lite modulation. Multiplexed signal paths and reconfigurable components are controlled for performance in GMSK and EDGE burst modes. Polar-lite EDGE modulation is programmed by setting a multiplexer coupling a first amplitude modulated signal path with a frequency modulated signal path input to a dual-mode power amplifier for amplification of the combined EDGE transmission signal. In full-polar EDGE modulation, amplitude modulated signal is multiplexed into a second amplitude modulated signal path for A/D conversion and comparison with a polar feedback signal coupled from the power amplifier output. The resulting comparison is applied to a power control port of the power amplifier to amplitude modulate the EDGE transmission output. Multiplexers are configured to disconnect the amplitude modulated paths when operating in GMSK signaling for both full-polar and polar-lite modulation.

Abstract: A CPU has a powerdown mode in which most of the circuitry does not receive power. Power-up, coming out of powerdown, is achieved in response to receiving an exception. Because most of the state information that is present in the CPU is not needed in response to an exception, there is no problem in removing power to most of the CPU during powerdown. The programmer's model register file and a few other circuits in the CPU are maintained in powerdown, but the vast majority of the circuits that make up the CPU: the execution unit, the instruction decode and control logic, instruction pipeline and bus interface, do not need to receive power. Removing power from these non-critical circuits results in significant power savings during powerdown. The powered circuits are provided with a reduced power supply voltage to provide additional power savings.

Abstract: Double gate transistors (12, 13) having different bottom gate dielectric thicknesses are formed on a first wafer (101) by forming a first gate dielectric layer (107); removing part of the first gate dielectric layer (107) from a first area (60); forming a second gate dielectric layer (108) to obtain a thinner bottom gate dielectric layer (150) over the first area (60) and a thicker bottom gate dielectric layer (151) over the second area (70); and forming a planar bottom gate layer (109) over first and second gate dielectric layers. After inverting and bonding the first wafer (101) to a second wafer (103), the bottom gate electrodes (109-2, 109-3), bottom gate dielectric layers (107, 108) and channel regions (203-2, 203-3) for the first and second double gate transistors (12, 13) are selectively etched prior to formation of the top gate structures.

Abstract: A Controller Area Network (CAN) node consists of a high-powered microcontroller, a low standby power regulator, a CAN bus transceiver, and a minimal CAN message buffer for storing received messages. Low power standby operation allows for the controller to power off, while the transceiver and regulator are operated in standby. The transceiver/regulator will enter run mode after the first symbol of a received CAN message is validated off the bus. As the original CAN message is received, it is buffered in the message buffer and, after stored, a status register is set to indicate the full message has been received. Once the controller has stabilized out of a wake-up mode, it retrieves the stored message and acts accordingly. The CAN message buffer is coupled to the controller by an system packet interface (SPI) interface for transmission of a controller wake-up command and retrieval of a buffered message.

Abstract: In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first plurality of values are accumulated in one or more accumulators. The one or more accumulators are accessed to obtain a first accumulated value and the first accumulated value is compared with a first expected accumulated value. In accordance with a second technique, a first plurality of load operations are performed at a processor to access data values stored in a first sequence of fields of a memory. The data values are accumulated in one or more accumulators of the processor to generate a first accumulated value and it is determined whether the memory has been corrupted based on a comparison of the first accumulated value to a first expected accumulation value.

Abstract: A system (28) includes a microelectronic device (10) including first transistors (22) and second transistors (24), a power supply (40) electrically connected to the first and second transistors to provide power to the first and second transistors such that current flows through the first and second transistors, a switch (32) in operable communication with the second transistors, the switch allowing current to flow from the power supply through the second transistors when in a first mode of operation and preventing current from flowing from the power supply through the second transistors when in a second mode of operation, control circuitry in operable communication with the switch, and current sensing circuitry coupled to the first transistors to detect a test amount of current flowing through at least one of the first transistors when the switch is in the first mode of operation.

Abstract: The transmitter comprises a signal generator including a capacitor producing the switched signal to be applied to the line. The capacitor is charged by a charging current in response to an input signal so as to define an edge of the switched signal through a feedback loop responsive to the capacitor voltage generating a feedback current having a continuous magnitude that is a progressive function of the capacitor voltage, the charging current being a function of the feedback current. The feedback loop generates first and second feedback voltages one of which is a rising function of the capacitor voltage and the other is a falling function of the capacitor voltage. The feedback current is generated first as a function of one of the feedback voltages and subsequently as a function of the other of the feedback voltages.

Abstract: A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor.

Abstract: A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that is manufactured by a method that includes determining a first transmission of a first light through a first pellicle, wherein the first light is normal to the first pellicle, determining a second transmission of a second light through the first pellicle, wherein the second light is not normal to the first pellicle, and modifying the first pellicle to form a second pellicle using the first and second transmission.

Abstract: A receiver and a method for channel estimation, the method includes calculating at least one initial channel estimate; characterized by calculating an estimate of the channel based upon a mathematical relationship between a first group of pilot subcarriers and a second group of pilot subcarriers; whereas a difference between locations of pilot subcarriers of the first group and locations of corresponding pilot subcarriers of the second group is substantially constant; and at least one of the following conditions are fulfilled: (i) pilot subcarriers that belong to the same group of subcarriers are non-evenly spaced in a frequency domain, (ii) a pilot subcarrier of the first group and a corresponding pilot subcarrier of the second group are proximate to each other in the frequency domain.