Abstract: A direct digital synthesizer (DDS) such as a Quantized Interpolated Edge Timed (QuIET) synthesizer is implemented in the feedback path of a translational Phase Lock Loop (PLL). The frequency translation introduced by the synthesizer reduces the amplification of reference feedback path noise sources, thereby enabling a wider loop bandwidth and improving high-pass filtering of phase noise without the addition of a second PLL.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate comprising silicon, forming a layer of dielectric on the surface of the semiconductor substrate, forming a gate electrode comprising silicon over the layer of dielectric, recessing the layer of dielectric under the gate electrode, filling the recess with a discrete charge storage material, oxidizing a portion of the gate electrode, and oxidizing a portion of the semiconductor substrate.

Abstract: A sensor unit for a three-axis accelerometer enabling reduction in chip size. The sensor unit is connected to an accelerometer that detects a plurality of acceleration values for a plurality of axis directions. The sensor unit includes a correction value generation circuit that sequentially generates a plurality of correction values for correcting the plurality of acceleration values. A correction circuit is connected to the correction value generation circuit to sequentially correct the plurality of acceleration values with a plurality of correction values and generate a plurality of corrected acceleration values.

Abstract: A method for dynamically determining frames required to build a complete picture in an MPEG video stream includes decoding an order of frames in the MPEG video stream according to a dependency vector model. The dependency vector model is configured for determining a dependency vector as a function of the decode order video stream for seamless operation over several types of MPEG streams. The method also includes performing frame accurate representations of the MPEG stream in a bidirectional fashion as a function of the dependency vector determined according to the dependency vector model.

Abstract: A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.

Abstract: A polish pad (40, 42) and platen (50) assembly for use in chemical mechanical polishing of semiconductor devices includes a platen (50) having a vented endpoint window (62, 72, 82) with one or more venting passageways (e.g., 64, 66) and/or a grooved or channeled platen surface (176) to prevent air pressure buildup in the air gap (46) by discharging or venting air through one or more vent pathways (52) formed in the platen to provide a pathway to ambient or sub-ambient environment. The air permeable construction of the vented endpoint window (72) provides pressure relief for the air gap (46) between the pad endpoint window (44) and the vented endpoint window (72), but may also include passages (75, 76) that are filled with an air permeable hydrophobic material which protects the underlying endpoint detection system (30, 32) from contamination during cleaning of the platen endpoint window (72).

Abstract: A device and a method for processing a frame, the method includes: receiving a frame; retrieving a lookup key parse command that includes an instruction field and an bitmap representative of selected frame fields to be searched in the frame; generating a lookup key by extracting at least one frame field if the type of the received frame matches an expected frame type; and looking up, using the lookup key, for additional frame processing instructions.

Abstract: A non-volatile memory device includes a voltage reference generator comprising a programmable voltage reference for generating a voltage signal having a programmable voltage level. In an embodiment, the programmable voltage reference provides the voltage signals for a wordline driver and/or a bitline current generator of the non-volatile memory device. The programmable voltage reference may comprise a Digital-to-Analog converter coupled between first and second supply voltages. A programmable current reference is also disclosed.

Abstract: A memory comprises a memory array and a plurality of clock driver circuits for providing a plurality of clock driver signals for timing an access to the memory array. A timing control circuit is coupled to the plurality of clock driver circuits. The timing control circuit includes a latch that is coupled to each of the plurality of clock driver circuits. The latch is for storing a logic state representative of a logic state of each of the plurality of clock driver signals in response to a first predetermined edge of a clock signal. The timing control circuit removes complex logic gates from the clock critical timing paths. Also, circuit topology is simplified allowing improved critical timing performance. Also, all of the clock driver circuits share a common latch control to improve clock recovery synchronization and reduce a risk of initializing the clock timing circuit in the wrong logic state.

Abstract: A clamping circuit of a DC/DC regulator includes a reference current generator to generate a reference current. The reference current can be based upon a specified maximum voltage across a bootstrap capacitor of the DC/DC regulator. The clamping circuit also includes a current generator that generates a current based on the voltage across the bootstrap capacitor. The current generated by the current generator is compared to the generated reference current. Based on the comparison, the voltage across the bootstrap capacitor is regulated. By regulating the voltage across the bootstrap capacitor based on current, rather than based directly on the voltage across the capacitor, the design of the clamping circuit is simplified compared to voltage-based implementations.

Abstract: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor stack is provided which includes a semiconductor substrate, a first semiconductor layer, and a first dielectric layer disposed between the substrate and the first semiconductor layer. A first trench is formed in the first dielectric layer which exposes a portion of the substrate, and a first implant region is formed in the first trench. Cathode and anode regions are formed in the first implant region.

Abstract: A device for detecting data synchronization in data communications includes pseudorandom noise (PN) lock circuits (101, 113, 127). The PN lock circuits (101, 113, 127) receive an input data stream (109). Each of the PN lock circuits (101, 113, 127) is time offset with respect to the other PN lock circuits. Each of the PN lock circuits (101, 113, 127) outputs a PN sequence responsive to the input data stream. For each PN lock circuit, there is provided a component (105, 117, 131) for comparing the PN sequence from the respective PN lock circuit to the input data stream, to determine whether the input data stream and the PN sequence are synchronized. An indication (107, 119, 133) that the data is synchronized is provided when the input data stream and the PN sequence are synchronized.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract: A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a latching type circuit such as a flip-flop or register prior to a power down operation to save power. The gate and first terminals of the two capacitors preferably share the same conductive line such as a polysilicon segment. A second transistor and a second set of capacitors store the complementary state of the logic state so that complementary signals are provided for detecting the stored logic state. After the time for power down has ended, the state of the semiconductor storage device made up of the two transistors and four capacitors is sensed, and the detected logic state is loaded back into the latching type circuit.

Abstract: A portion of a memory may include a first memory block, including a first memory cell coupled to a first memory data line, a second memory block, including a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line.

Abstract: A semiconductor fabrication method includes forming a semiconductor structure including source/drain regions disposed on either side of a channel body wherein the source/drain regions include a first semiconductor material and wherein the channel body includes a migration barrier of a second semiconductor material. A gate dielectric overlies the semiconductor structure and a gate module overlies the gate dielectric. An offset in the majority carrier potential energy level between the first and second semiconductor materials creates a potential well for majority carriers in the channel body. The migration barrier may be a layer of the second semiconductor material over a first layer of the first semiconductor material and under a capping layer of the first semiconductor material. In a one dimensional migration barrier, the migration barrier extends laterally through the source/drain regions while, in a two dimensional barrier, the barrier terminates laterally at boundaries defined by the gate module.

Abstract: A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.

Abstract: A semiconductor fabrication process includes forming a gate electrode (112) overlying a gate dielectric (114) overlying a semiconductor substrate (104) of a wafer (101) and a liner dielectric layer (116) including vertical portions (118) adjacent sidewalls of the gate electrode and horizontal portions (117) overlying an upper surface of the semiconductor substrate (104). A spacer (108) is formed adjacent a vertical portion (118) and overlying a horizontal portion (117) of the liner dielectric layer (116). After forming the spacer (108), exposed portions of the liner dielectric layer (116) are removed to form a liner dielectric structure (126) covered by the extension spacer (108). The extension spacer (108) is then etched back to expose or uncover extremities of the liner dielectric structure (126). Prior to etching back the spacer (108), a metal (130) may be sputtered deposited over the wafer (101) preparatory to forming a silicide (134).

Abstract: Method and system for tuning a tunable antenna uses a comparison between a signal response at two different tuning frequencies to determine how or if the tuning needs to be further adjusted. With the approach, the method and system arrive at a frequency shift that is centered about the desired antenna frequency, which point there is no net change in the signal response. In a further aspect, a frequency to which a tuned antenna is tuned is shifted to verify whether the antenna is still in tune. Modifications to minimize disturbance of the output received signal that would otherwise be caused by the frequency shifting are contemplated.

Abstract: A method for making a composite integrated device includes providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region and is at a surface of the first integrated device. The method further includes forming a sidewall spacer along a sidewall of a first opening in a first dielectric layer, located over the surface of the integrated device, and providing a deformable metal feature adjacent to the sidewall spacer and in the first opening. The method further includes providing a second integrated device having a substrate, an overlying interconnect region, a contact, and a second dielectric layer surrounding the contact of the second integrated device. The method further includes contacting the contact of the second integrated device with the deformable metal feature and pressing the first dielectric layer against the second dielectric layer.