Patents Assigned to Freescale
  • Tunable antifuse element and method of manufacture
    Patent number: 7528015
    Abstract: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Patrice M. Parris, Weize Chen, John M. McKenna, Jennifer H. Morrison, Moaniss Zitouni, Richard J. De Souza
  • Stressor integration and method thereof
    Patent number: 7528029
    Abstract: A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor layer. A second stressor layer (219) is formed over the sacrificial layer.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Darren V. Goedekc, John J. Hackenberg
  • Class-D amplifier with noise-immunity feedback
    Patent number: 7528653
    Abstract: A class-D amplifier includes a switching transistor section, a filter, an analog to digital converter, and a feedback module. The switching transistor section is operably coupled to convert a serial input into a switched output signal. The filter is operably coupled to filter the switched output signal to produce an output of the class-D amplifier. The analog to digital converter is operably coupled to convert an analog input into a multi-bit digital signal based on a feedback signal, wherein the serial input corresponds to the multi-bit digital signal. The feedback module is operably coupled to the produce the feedback signal based on at least one varying property of the switching transistor section.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Marcus W. May
  • Methods and apparatus for simulating distributed effects
    Patent number: 7530039
    Abstract: In general, various embodiments of the present invention relate to systems and methods for simulating distributed effects by providing a meshing pattern (200) (e.g., a two-dimensional meshing pattern that is part of a recognition layer), applying that meshing pattern to the physical layout (100), and partitioning the physical layout into a three-dimensional netlist (300) of components derived from the unit cells defined by the meshing pattern (200), thereby modeling the parasitics within the design.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Margaret L. Kniffin, Dmitry S. Shipitsin, Michael J. Zunino
  • Capacitor assembly with shielded connections and method for forming the same
    Patent number: 7528468
    Abstract: A capacitor assembly (82) is formed on a substrate (20). The capacitor assembly a first conductive plate (38) and a second conductive plate (60) formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance. A conductive trace (40) is formed over the substrate that is connected to the first conductive plate and extends away from the capacitor assembly. A conductive shield (62) is formed over at least a portion of the conductive trace that is separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the conductive trace.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Andrew C. McNeil, Dubravka Bilic, Stephen R. Hooper
  • Tone detector and method therefor
    Patent number: 7529363
    Abstract: A tone detector able to detect multicomponent tones for various tone formats is disclosed. An input signal is received and frequency and amplitude components, if any, of each sample of the incoming signal are estimated. In estimating the components, a current digit value is used to appropriately filter the input signal and estimate frequency and amplitude components. Using the component estimates, a new digit value is determined using a table in storage corresponding to the current tone format. The new digit value corresponds to the symbol whose components are closest in value to the estimated components corresponding to the current digit value. The new digit value is fed back as the current digit value and used in combination with a next sample of the input signal to determine a new digit value. A decision unit is used to process the digit values to determine when a valid symbol is detected.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lucio F. C. Pessoa, Valentin Emiya, David Melles, Delphine Vallot
  • Self-aligned split gate memory cell and method of forming
    Patent number: 7528047
    Abstract: A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rajesh A. Rao, Tushar P. Merchant, Ramachandran Muralidhar, Lakshmanna Vishnubhotla
  • Fine pitch interconnect and method of making
    Patent number: 7528069
    Abstract: Fine pitch contacts are achieved by using traces that extend to the contacts without requiring capture pads at the contact pads. Capture pads are desirably avoided because they have a diameter greater than the line to which they are attached. Preferably, adjacent contact pads are present in the same opening in the dielectric. The traces to the contact pads are in a line so that no widening is required where the lines make contact to the contact pads. The lines can be widened before they get to the contact pads but at the contact pads, they are substantially at the minimum width for the line. Thus, the contact pads can be at a pitch much lower than if capture pads were used.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert J. Wenzel, George R. Leal
  • Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer
    Patent number: 7528078
    Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique. The process can further include densifying the nitride layer. The process can still further include removing a part of the nitride layer, wherein a remaining portion of the nitride layer can lie within the opening and be spaced apart from the surface.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: May 5, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Toni D. Van Gompel, Kuang-Hsin Chen, Laegu Kang, Rode R. Mora, Michael D. Turner
  • Process of forming an electronic device including an inductor
    Patent number: 7524731
    Abstract: An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached to the conductive traces over the shock-absorbing layer. In another aspect, a process can be used to form the electronic device including the inductor. In still another aspect, an electronic device can a toroidal-shaped inductor that includes linear inductor segments that are connected in series.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventor: James Jen-Ho Wang
  • RF power transistor device with metal electromigration design and method thereof
    Patent number: 7525152
    Abstract: An RF power transistor with a metal design (70) comprises a drain pad (72) and a plurality of metal drain fingers (74) extending from the drain pad, wherein at least one metal drain finger comprises one or more sections of metal (74-1, 74-2, 100-1, 100-2, 100-3), each section of metal including of one or more branch (54-1, 54-2, 116-1, 116-2, 116-11, 116-21, 116-41) of metal having a metal width maintained within a bamboo regime.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christopher P. Dragon, Wayne R. Burger, Robert A. Pryor
  • Storage circuit and method therefor
    Patent number: 7525867
    Abstract: Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, Prashant U. Kenkare, Jeremiah T. C. Palmer
  • Modified hybrid orientation technology
    Patent number: 7524707
    Abstract: A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Olubunmi O. Adetutu, Mariam G. Sadaka, Ted R. White, Bich-Yen Nguyen
  • Brown out detector
    Patent number: 7525353
    Abstract: A brown out detector includes a first resistive element connected to a first voltage and a first node. A capacitor is connected to the first node and a second voltage. The detector also includes a second transistor and a third transistor. The second transistor has a drain connected to a second node, a source connected to the first node, and a gate connected to the first voltage. The third transistor has a source connected to the second voltage and the capacitor, a drain connected to the second node, and a gate connected to the first voltage. The detector also includes a latch having an input connected to the second node and a detector output, which generates a reset signal when the first voltage is less than a detection threshold voltage.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sanjay Kumar Wadhwa, Siddhartha G.K.
  • Memory circuit
    Patent number: 7525866
    Abstract: A memory includes a plurality of memory arrays. Each of the plurality of memory arrays includes a plurality of sub-arrays. A plurality of power supply conductors are provided over the memory for supplying power to the plurality of memory arrays. When accessing the memory to simultaneously read a plurality of bits from the memory, the sub-arrays are accessed so as to provide a relatively uniform current demand on the plurality of power supply conductors. In one embodiment, the accessed sub-arrays are organized so that sides, or edges, of each accessed sub-array are not adjacent to each other.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Andrew C. Russell
  • Method of making self-aligned split gate memory cell
    Patent number: 7524719
    Abstract: A method for forming a split gate memory cell (10,11) using a semiconductor substrate (12) includes forming a select gate structure (48) and a sacrificial structure (50) over the substrate. An opening is between the select gate structure and the sacrificial structure. The opening is lined with a storage layer (56,168). The opening is further filled with select gate material (58,170). The sacrificial structure is removed after filling the opening with the select gate material.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Ko-Min Chang
  • Method and apparatus for forming an electrical connection to a semiconductor substrate
    Patent number: 7524693
    Abstract: A device (100) may use one or more conductive elements (112) to electrically couple a substrate (116) and a cap (114). In one embodiment, an acceleration sense element may be formed on the substrate (116), and the cap (114) may be used to provide hermetic protection to the acceleration sense element. In one embodiment, conductive elements (112) may be formed by dispensing conductive die attach material. Wire bonds (e.g. 322) bonded to bond pads (e.g. 332) on the substrate (e.g. 316) may be used to couple substrate (116), the conductive element pad (335), and the cap (114), to a desired predetermined potential.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: April 28, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Peter S. Schultz
  • METHOD FOR DRIVING A PTC ELECTRICAL LOAD ELEMENT
    Publication number: 20090102400
    Abstract: A method is intended to make it possible to drive a PTC electrical load element with a switching unit with the highest possible operational reliability. For this purpose, the electric current is switched off if a predetermined current threshold value is exceeded, the magnitude of the current threshold value being determined from the operating parameters of the load element.
    Type: Application
    Filed: April 16, 2007
    Publication date: April 23, 2009
    Applicant: Freescale Semiconductor Inc.
    Inventors: Laurent Guillot, Kamel Abouda, Philippe Rosado, Helmut Henssler, Uli Joos, Josef Schnell, Norbert Stuhler
  • Minimum memory operating voltage technique
    Patent number: 7523373
    Abstract: A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: April 21, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Andrew C. Russell, David R. Bearden, Bradford L. Hunter, Shayan Zhang
  • Semiconductor optical devices having fin structures
    Patent number: 7521720
    Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: April 21, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, Yang Du, Voon-Yew Thean